bcd2.tan.qmsg

来自「verilogHDL 入门的小程序」· QMSG 代码 · 共 6 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 11 12:06:38 2008 " "Info: Processing started: Fri Jul 11 12:06:38 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off BCD2 -c BCD2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off BCD2 -c BCD2 --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "data_in\[3\] data_out\[1\] 11.504 ns Longest " "Info: Longest tpd from source pin \"data_in\[3\]\" to destination pin \"data_out\[1\]\" is 11.504 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns data_in\[3\] 1 PIN PIN_50 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_50; Fanout = 4; PIN Node = 'data_in\[3\]'" {  } { { "D:/prj/BCD2/db/BCD2_cmp.qrpt" "" { Report "D:/prj/BCD2/db/BCD2_cmp.qrpt" Compiler "BCD2" "UNKNOWN" "V1" "D:/prj/BCD2/db/BCD2.quartus_db" { Floorplan "D:/prj/BCD2/" "" "" { data_in[3] } "NODE_NAME" } "" } } { "BCD2.v" "" { Text "D:/prj/BCD2/BCD2.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.787 ns) + CELL(0.590 ns) 7.846 ns data_out~200 2 COMB LC_X1_Y13_N6 1 " "Info: 2: + IC(5.787 ns) + CELL(0.590 ns) = 7.846 ns; Loc. = LC_X1_Y13_N6; Fanout = 1; COMB Node = 'data_out~200'" {  } { { "D:/prj/BCD2/db/BCD2_cmp.qrpt" "" { Report "D:/prj/BCD2/db/BCD2_cmp.qrpt" Compiler "BCD2" "UNKNOWN" "V1" "D:/prj/BCD2/db/BCD2.quartus_db" { Floorplan "D:/prj/BCD2/" "" "6.377 ns" { data_in[3] data_out~200 } "NODE_NAME" } "" } } { "BCD2.v" "" { Text "D:/prj/BCD2/BCD2.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.534 ns) + CELL(2.124 ns) 11.504 ns data_out\[1\] 3 PIN PIN_18 0 " "Info: 3: + IC(1.534 ns) + CELL(2.124 ns) = 11.504 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'data_out\[1\]'" {  } { { "D:/prj/BCD2/db/BCD2_cmp.qrpt" "" { Report "D:/prj/BCD2/db/BCD2_cmp.qrpt" Compiler "BCD2" "UNKNOWN" "V1" "D:/prj/BCD2/db/BCD2.quartus_db" { Floorplan "D:/prj/BCD2/" "" "3.658 ns" { data_out~200 data_out[1] } "NODE_NAME" } "" } } { "BCD2.v" "" { Text "D:/prj/BCD2/BCD2.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.183 ns 36.36 % " "Info: Total cell delay = 4.183 ns ( 36.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.321 ns 63.64 % " "Info: Total interconnect delay = 7.321 ns ( 63.64 % )" {  } {  } 0}  } { { "D:/prj/BCD2/db/BCD2_cmp.qrpt" "" { Report "D:/prj/BCD2/db/BCD2_cmp.qrpt" Compiler "BCD2" "UNKNOWN" "V1" "D:/prj/BCD2/db/BCD2.quartus_db" { Floorplan "D:/prj/BCD2/" "" "11.504 ns" { data_in[3] data_out~200 data_out[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.504 ns" { data_in[3] data_in[3]~out0 data_out~200 data_out[1] } { 0.000ns 0.000ns 5.787ns 1.534ns } { 0.000ns 1.469ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 11 12:06:38 2008 " "Info: Processing ended: Fri Jul 11 12:06:38 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}