bcd2.map.qmsg

verilogHDL 入门的小程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 11 12:06:25 2008 " "Info: Processing started: Fri Jul 11 12:06:25 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BCD2 -c BCD2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BCD2 -c BCD2" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCD2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file BCD2.v" { { "Info" "ISGN_ENTITY_NAME" "1 BCD2 " "Info: Found entity 1: BCD2" {  } { { "BCD2.v" "" { Text "D:/prj/BCD2/BCD2.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "BCD2 " "Info: Elaborating entity \"BCD2\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "data_out\[5\] GND " "Warning: Pin \"data_out\[5\]\" stuck at GND" {  } { { "BCD2.v" "" { Text "D:/prj/BCD2/BCD2.v" 5 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_out\[6\] GND " "Warning: Pin \"data_out\[6\]\" stuck at GND" {  } { { "BCD2.v" "" { Text "D:/prj/BCD2/BCD2.v" 5 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_out\[7\] GND " "Warning: Pin \"data_out\[7\]\" stuck at GND" {  } { { "BCD2.v" "" { Text "D:/prj/BCD2/BCD2.v" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "18 " "Info: Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "5 " "Info: Implemented 5 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 11 12:06:26 2008 " "Info: Processing ended: Fri Jul 11 12:06:26 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}