bcd2.map.eqn

verilogHDL 入门的小程序

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--A1L61 is data_out~199
--operation mode is normal

A1L61 = EN & data_in[0];


--A1L71 is data_out~200
--operation mode is normal

A1L71 = EN & (data_in[1] & (!data_in[3]) # !data_in[1] & data_in[2] & data_in[3]);


--A1L81 is data_out~201
--operation mode is normal

A1L81 = EN & data_in[2] & (data_in[1] # !data_in[3]);


--A1L91 is data_out~202
--operation mode is normal

A1L91 = EN & data_in[3] & !data_in[1] & !data_in[2];


--A1L02 is data_out~203
--operation mode is normal

A1L02 = data_in[3] & (data_in[1] # data_in[2]) # !EN;


--EN is EN
--operation mode is input

EN = INPUT();


--data_in[0] is data_in[0]
--operation mode is input

data_in[0] = INPUT();


--data_in[2] is data_in[2]
--operation mode is input

data_in[2] = INPUT();


--data_in[1] is data_in[1]
--operation mode is input

data_in[1] = INPUT();


--data_in[3] is data_in[3]
--operation mode is input

data_in[3] = INPUT();


--data_out[0] is data_out[0]
--operation mode is output

data_out[0] = OUTPUT(A1L61);


--data_out[1] is data_out[1]
--operation mode is output

data_out[1] = OUTPUT(A1L71);


--data_out[2] is data_out[2]
--operation mode is output

data_out[2] = OUTPUT(A1L81);


--data_out[3] is data_out[3]
--operation mode is output

data_out[3] = OUTPUT(A1L91);


--data_out[4] is data_out[4]
--operation mode is output

data_out[4] = OUTPUT(A1L02);


--data_out[5] is data_out[5]
--operation mode is output

data_out[5] = OUTPUT(GND);


--data_out[6] is data_out[6]
--operation mode is output

data_out[6] = OUTPUT(GND);


--data_out[7] is data_out[7]
--operation mode is output

data_out[7] = OUTPUT(GND);