bcd2.tan.rpt

verilogHDL 入门的小程序

Timing Analyzer report for BCD2
Fri Jul 11 12:06:38 2008
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                              ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From       ; To          ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 11.504 ns   ; data_in[3] ; data_out[1] ;            ;          ; 0            ;
; Total number of failed paths ;       ;               ;             ;            ;             ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------+
; tpd                                                                    ;
+-------+-------------------+-----------------+------------+-------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From       ; To          ;
+-------+-------------------+-----------------+------------+-------------+
; N/A   ; None              ; 11.504 ns       ; data_in[3] ; data_out[1] ;
; N/A   ; None              ; 11.501 ns       ; data_in[3] ; data_out[4] ;
; N/A   ; None              ; 11.498 ns       ; data_in[3] ; data_out[2] ;
; N/A   ; None              ; 11.495 ns       ; data_in[3] ; data_out[3] ;
; N/A   ; None              ; 11.287 ns       ; data_in[2] ; data_out[1] ;
; N/A   ; None              ; 11.279 ns       ; data_in[2] ; data_out[3] ;
; N/A   ; None              ; 11.278 ns       ; data_in[2] ; data_out[4] ;
; N/A   ; None              ; 11.271 ns       ; data_in[2] ; data_out[2] ;
; N/A   ; None              ; 11.190 ns       ; data_in[1] ; data_out[1] ;
; N/A   ; None              ; 11.184 ns       ; data_in[1] ; data_out[4] ;
; N/A   ; None              ; 11.182 ns       ; data_in[1] ; data_out[3] ;
; N/A   ; None              ; 11.178 ns       ; data_in[1] ; data_out[2] ;
; N/A   ; None              ; 11.115 ns       ; EN         ; data_out[4] ;
; N/A   ; None              ; 11.114 ns       ; EN         ; data_out[1] ;
; N/A   ; None              ; 11.112 ns       ; EN         ; data_out[2] ;
; N/A   ; None              ; 11.103 ns       ; EN         ; data_out[3] ;
; N/A   ; None              ; 10.999 ns       ; EN         ; data_out[0] ;
; N/A   ; None              ; 10.694 ns       ; data_in[0] ; data_out[0] ;
+-------+-------------------+-----------------+------------+-------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Fri Jul 11 12:06:38 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off BCD2 -c BCD2 --timing_analysis_only
Info: Longest tpd from source pin "data_in[3]" to destination pin "data_out[1]" is 11.504 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_50; Fanout = 4; PIN Node = 'data_in[3]'
    Info: 2: + IC(5.787 ns) + CELL(0.590 ns) = 7.846 ns; Loc. = LC_X1_Y13_N6; Fanout = 1; COMB Node = 'data_out~200'
    Info: 3: + IC(1.534 ns) + CELL(2.124 ns) = 11.504 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'data_out[1]'
    Info: Total cell delay = 4.183 ns ( 36.36 % )
    Info: Total interconnect delay = 7.321 ns ( 63.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Jul 11 12:06:38 2008
    Info: Elapsed time: 00:00:01