bcd2.fit.eqn

verilogHDL 入门的小程序

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--A1L61 is data_out~199 at LC_X1_Y13_N8
--operation mode is normal

A1L61 = EN & data_in[0];


--A1L71 is data_out~200 at LC_X1_Y13_N6
--operation mode is normal

A1L71 = EN & (data_in[3] & !data_in[1] & data_in[2] # !data_in[3] & data_in[1]);


--A1L81 is data_out~201 at LC_X1_Y13_N2
--operation mode is normal

A1L81 = EN & data_in[2] & (data_in[1] # !data_in[3]);


--A1L91 is data_out~202 at LC_X1_Y13_N5
--operation mode is normal

A1L91 = data_in[3] & EN & !data_in[1] & !data_in[2];


--A1L02 is data_out~203 at LC_X1_Y13_N4
--operation mode is normal

A1L02 = data_in[3] & (data_in[1] # data_in[2]) # !EN;


--EN is EN at PIN_46
--operation mode is input

EN = INPUT();


--data_in[0] is data_in[0] at PIN_47
--operation mode is input

data_in[0] = INPUT();


--data_in[2] is data_in[2] at PIN_49
--operation mode is input

data_in[2] = INPUT();


--data_in[1] is data_in[1] at PIN_48
--operation mode is input

data_in[1] = INPUT();


--data_in[3] is data_in[3] at PIN_50
--operation mode is input

data_in[3] = INPUT();


--data_out[0] is data_out[0] at PIN_17
--operation mode is output

data_out[0] = OUTPUT(A1L61);


--data_out[1] is data_out[1] at PIN_18
--operation mode is output

data_out[1] = OUTPUT(A1L71);


--data_out[2] is data_out[2] at PIN_19
--operation mode is output

data_out[2] = OUTPUT(A1L81);


--data_out[3] is data_out[3] at PIN_20
--operation mode is output

data_out[3] = OUTPUT(A1L91);


--data_out[4] is data_out[4] at PIN_21
--operation mode is output

data_out[4] = OUTPUT(A1L02);


--data_out[5] is data_out[5] at PIN_23
--operation mode is output

data_out[5] = OUTPUT(GND);


--data_out[6] is data_out[6] at PIN_41
--operation mode is output

data_out[6] = OUTPUT(GND);


--data_out[7] is data_out[7] at PIN_42
--operation mode is output

data_out[7] = OUTPUT(GND);