bcd2.fit.rpt

verilogHDL 入门的小程序

; data_in[0]   ; 1                ;
; data_out~203 ; 1                ;
; data_out~202 ; 1                ;
; data_out~201 ; 1                ;
; data_out~200 ; 1                ;
; data_out~199 ; 1                ;
+--------------+------------------+


+----------------------------------------------------+
; Interconnect Usage Summary                         ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage                 ;
+----------------------------+-----------------------+
; C4s                        ; 18 / 16,320 ( < 1 % ) ;
; Direct links               ; 0 / 21,944 ( 0 % )    ;
; Global clocks              ; 0 / 8 ( 0 % )         ;
; LAB clocks                 ; 0 / 240 ( 0 % )       ;
; LUT chains                 ; 0 / 5,382 ( 0 % )     ;
; Local interconnects        ; 10 / 21,944 ( < 1 % ) ;
; M4K buffers                ; 0 / 720 ( 0 % )       ;
; R4s                        ; 1 / 14,640 ( < 1 % )  ;
+----------------------------+-----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 5.00) ; Number of LABs  (Total = 1) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 0                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 1                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 5.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 5.00) ; Number of LABs  (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 0                           ;
; 2                                               ; 0                           ;
; 3                                               ; 0                           ;
; 4                                               ; 0                           ;
; 5                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 5.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Fri Jul 11 12:06:27 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off BCD2 -c BCD2
Info: Selected device EP1C6Q240C8 for design "BCD2"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EP1C12Q240C8 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin data_out[5] has GND driving its datain port
    Info: Pin data_out[6] has GND driving its datain port
    Info: Pin data_out[7] has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jul 11 12:06:33 2008
    Info: Elapsed time: 00:00:06