top_tuner.v

Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.

// Top_Tuner.v

// step up and down inputs should have a width of one clock cycle.
// This block should be placed in the external feedback path of Actel PLL. 
// The gate level macros in this design are generated from ACTGEN using ProASICPlus macro library. The device
// specific blocks are "INCR" and "DECR" sub-modules

module Top_Tuner (pllout_clk, step_up, step_dn, rst_n, pll_extfb_in);

// Tuner Parameters. The Min and Max values correspond to the maximum and minimum frequency respectively
parameter STEP_VALUE_MIN = 50; // minimum number of clock cycles with one clcok cycle masked out
parameter STEP_VALUE_MAX = 60;  //maximum number of clock cycles with one clcok cycle masked out
parameter INITIATE_VALUE  = 55; //number of clock cycles with one clcok cycle masked out at reset
parameter WIDTH = 8;

input pllout_clk; //Clock output of the PLL 
input step_up, step_dn; //Command inputs (one clock cycle wide) to step up or down the frequency
input rst_n; // Active low global reset
output pll_extfb_in; // Output of the tuner block should be input to the PLL external feedback port


wire mask;
wire [11:0] step_value;

// Clock Masking Block: This block is made of a simple AND gate
Mask_Block mask_clk (.clk_in(pllout_clk), .mask(mask), .clk_out(pll_extfb_in));

//Stepper block receives the step up/dn commands and passes appropriate pulse count value to the counter
stepper #(STEP_VALUE_MIN,STEP_VALUE_MAX,INITIATE_VALUE,WIDTH) stepper_block (.clk(pllout_clk), .step_up(step_up), .step_dn(step_dn), 
                       .rst_n(rst_n), .step_value(step_value));

// Counts the number of pulses defined by the stepper block and passes a mask command after each count cycle
// to the mask block.
counter_dec #(WIDTH,INITIATE_VALUE) counter_block (.clk(pllout_clk), .load(step_value),  .rst_n(rst_n), .mask_out(mask));


endmodule