incr.v

来自「Clock_Dithering_Verilog this is a Clock 」· Verilog 代码 · 共 15 行

module INCR(DataA, Sum);
  parameter WIDTH = 8;
  input [WIDTH-1:0] DataA;
  output [WIDTH-1:0] Sum;
  reg [WIDTH-1:0] Sum;

  always @ (DataA)
  begin

    Sum = DataA + 1;

  end

endmodule