decr.v

来自「Clock_Dithering_Verilog this is a Clock 」· Verilog 代码 · 共 20 行

module DECR (DataA, Sum, Cout);
  parameter WIDTH = 8;
  input [WIDTH-1:0] DataA;
  output [WIDTH-1:0] Sum;
  reg [WIDTH_1:0] Sum;
  output Cout;
  reg Cout;
  reg carry;

  always @ (DataA)
  begin

    {carry,Sum} = DataA - 1;

    Cout = !carry;

  end

endmodule