stepper.v

来自「Clock_Dithering_Verilog this is a Clock 」· Verilog 代码 · 共 46 行

// Stepper.v
// This block is to process the step up/down commands and pass it appopriately to the clock pulse counter
// Step_up command has priority over Step_dn if asserted at the same time

module stepper (clk, step_up, step_dn, rst_n, step_value);

// Step parameters
parameter STEP_VALUE_MIN = 10; // minimum number of clock cycles with one clcok cycle masked out
parameter STEP_VALUE_MAX = 110;  //maximum number of clock cycles with one clcok cycle masked out
parameter INITIATE_VALUE  = 55; //number of clock cycles with one clcok cycle masked out at reset
parameter WIDTH = 8;

input clk;  //Clock input
input step_up, step_dn; // Frequency up/down commands
input rst_n; // Active-low global reset
output [11:0] step_value; //Pulse count number input to the pulse counter

reg [WIDTH-1:0] step_value_int;
wire [WIDTH-1:0] step_velue_dec, step_value_inc;

INCR #(WIDTH) step_inc(.DataA(step_value_int),.Sum(step_value_inc));
DECR #(WIDTH) step_dec(.DataA(step_value_int),.Sum(step_velue_dec),.Cout());


// defining the step value based on the input command and current step value
always @ (posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
       step_value_int <= INITIATE_VALUE;
else if ((step_up == 1'b1) && (step_value_int != STEP_VALUE_MIN))
  step_value_int <=  step_velue_dec;
else if ((step_dn == 1'b1) && (step_value_int != STEP_VALUE_MAX))
  step_value_int <= step_value_inc;
else
 step_value_int <= step_value_int;
end 

assign step_value = step_value_int;


endmodule