mask.v

来自「Clock_Dithering_Verilog this is a Clock 」· Verilog 代码 · 共 8 行

// Mask.v
module Mask_Block (clk_in, mask, clk_out);
input clk_in, mask;
output clk_out;

assign clk_out = clk_in & mask;

endmodule