counter_dec.v

来自「Clock_Dithering_Verilog this is a Clock 」· Verilog 代码 · 共 46 行

// counter_dec.v
// The counter block is decremental. 
// The load value is loaded into the counter only at the end of each count cycle. 
module counter_dec (clk, load,  rst_n, mask_out);

parameter WIDTH = 8;
parameter INITIAL_VALUE = 55;

input clk;
input [WIDTH-1:0] load;
input rst_n;
output mask_out;

reg [WIDTH-1:0] dec;
wire [WIDTH-1:0] dec_int;
reg mask_int;
wire mask;

//  Counter block using a Decrement block.
//  Only loads when the count cycle is over. Count cycle is flagged by the active-low carry output of the
// decrementer block (mask signal)
always @ (posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0) 
 dec <= (INITIATE_VALUE - 1);
else if (mask == 1'b0)
 dec <= (load - 1);
else
 dec <= dec_int;
end 

DECR #(WIDTH) decrement(.DataA(dec),.Sum(dec_int),.Cout(mask));


// End of each count cycle is flagged by mask signal and is registers before being passed to the mask block.
always @ (posedge clk  or negedge rst_n)
begin
if (rst_n ==1'b0)
mask_int <= 1'b1;
else 
mask_int <= mask;
end

assign mask_out = mask_int;

endmodule