tb_dct.v

arm7内核的verilog代码

`timescale 1ns/100ps
`define P 20
module tb_dct;

  reg clk, rst_b, d_rdy;
  reg [1:0] start;
  reg [7:0] d_in;
  wire calc_done, d_en, w1_done, w2_done;
  wire [15:0] d_out;
  
  
  dct dct0(.clk(clk), .rst_b(rst_b), .start(start), .d_rdy(d_rdy),
           .d_in(d_in), .calc_done(calc_done),.d_en(d_en),.d_out(d_out),  .w1_done(w1_done), .w2_done(w2_done) );

  initial begin	 //clk generator
	clk=1'b1;
	forever #(`P/2) clk=~clk;
  end

  integer i;
  
     
   
  initial begin	 //stimulus
	rst_b=1'b1;
	start=2'b00;
        d_rdy=0;
        d_in =0;
	#(`P*2);   //reset
	rst_b=1'b0;
	#(`P*3);	//IN_1
	rst_b=1'b1;
	#(`P*2+`P/2);
        start=2'b01;
 	#(5*`P);
        start=2'b00;
        
        d_rdy = 1'b1;
        
        for(i=0;i<=63;i=i+1) begin
           d_in = i;
           #(`P);
        end   
           
        // @(posedge w1_done);
        d_rdy =1'b0;
        d_in = 0; 
                 
        #(10*`P);
        start=2'b10;
	#(2*`P); 
	start=2'b00;  
        d_rdy = 1'b1;
        
        for(i=0;i<=63;i=i+1) begin
          d_in = i; #(`P);
        end   
            
        //@( posedge w2_done );
        #(10*`P);  d_rdy = 0;
        d_in = 0;
         #(2*`P); 
        start=2'b11;
        #(2*`P);  
        start=2'b00;
        @( posedge calc_done );
        #(10*`P)  $finish(2);
  end

     
endmodule