dct.v.bak

arm7内核的verilog代码

//dct.v
module dct(clk,rst_b,d_rdy,start,d_in,calc_done,d_en,d_out);
  input clk, rst_b, d_rdy;
  input [1:0]start;
  wire [1:0]start;
  d_in [7:0]d_in;
  wire [7:0]d_in;
  output calc_done,d_en;
  reg calc_done,d_en;
  output [15:0]d_out;
  wire [15:0]d_out;
  
  parameter NOP = 2'b00, IN_1 = 2'b01, IN2 = 2'b10, CALC = 2'b11;
  reg [1:0] st_p, st_n;
  reg [5:0] cnt_p, cnt_n;
  
  
  always @(posedge clk)  // state update
    if(~rst_b)
      st_p <= NOP;
    else st_p <= st_n;
    
  always @(posedge clk) begin // state machine output
    if(!rst_b) begin
      cnt_p<=6'b0;
      d_en<=1'b0;
      calc_done<=1'b0;		
    end else begin
      cnt_p<=cnt_n;
      d_en_p<=d_en_n;
      calc_done<=calc_done_n;		
    end
  end
  
  always @(st_p or cmd or cnt_p) begin	//next state
    d_en_n=1'b0;
    calc_done_n=1'b0;
    st_n=NOP;
    cnt_n=6'b0;	
    case(st_p)	//synopsys full_case parallel_case
      2'b00: begin  // NOP
	 if(start==IN_1) begin
	    st_n=IN_1;
	    cnt_n=6'b0;
	    cen_n=1'b0;
	    wen_n=1'b0;
	   
	 end else if(start==IN_2) begin
	    st_n=IN_2;
	    cnt_n=6'b0;
	    cen_n=1'b0;
	    wen_n=1'b1;
	   
         end else if(start==CALC) begin
            st_n=CALC;
            cnt_n=6'b0;
           				
         end
      end
      2'b01: begin  // data01 input
	 if(cnt_p==6'd63) begin	//return NOP
	    w_done_n=1'b1;				
	 end else if(d_rdy) begin
	    st_n=WRITE;
	    cnt_n=cnt_p+1'b1;
	    cen_n=1'b0;   // select ram01
	    wen_n=1'b0;   // write			
         end else begin
	    st_n=WRITE; 
	 end
      end
      2'b10: begin  // data02 input
	 if(cnt_p==6'd63) begin	//IDLE
	    r_done_n=1'b1;
	    //st_n=IDLE;
	    //cnt_n=6'b0;
	   //cen_n=1'b1;
	   //wen_n=1'b0;
	 end else begin
	    st_n=READ;
	    cnt_n=cnt_p+1'b1;
	    cen_n=1'b0;
	    wen_n=1'b1;			
	 end		
      end
      2'b11: begin    //calt
	 if(cnt_p==6'd63) begin	//IDLE
	    r_done_n=1'b1;
	 end else begin
	    st_n=READ;
	    cnt_n=cnt_p+1'b1;
	    cen_n=1'b0;
	    wen_n=1'b1;			
	 end		
      end
    endcase
  end
  
  sram_64X8	u01_sram_64X8(.Q(q),.CLK(clk),.CEN(cen_p),.WEN(wen_p),.A(addr),.D(din),.OEN(1'b0));
  sram_64X8	u02_sram_64X8(.Q(q),.CLK(clk),.CEN(cen_p),.WEN(wen_p),.A(addr),.D(din),.OEN(1'b0));
   
   
  wire	[5:0] addr;
  wire	[7:0] din;
  
  assign addr=cnt_p;
  
endmmodule