dct.ttt

arm7内核的verilog代码

//dct.v
module dct( clk,  rst_b,  d_rdy,  start,  d_in, 
                    calc_done,  d_en,  d_out, w1_done, w2_done);
  input clk, rst_b, d_rdy;
  wire clk, rst_b, d_rdy;
  input [1:0]start;
  wire [1:0]start;
  input [7:0]d_in;
  wire [7:0]d_in;
  output calc_done,d_en,w1_done, w2_done;
  reg  calc_done, d_en,w1_done, w2_done;
  output [18:0]d_out;
  wire [18:0]d_out;
  

  
  wire [7:0] q_1, q_2; 
  parameter NOP = 2'b00, IN_1 = 2'b01, IN_2 = 2'b10, CALC = 2'b11;
  reg [1:0]  st_p, st_n;        // current maching state ,  next machine state
  reg [5:0]  cnt1_p, cnt1_n, cnt2_p, cnt2_n ;   // counter for chip1 ,  chip2
  reg cen1_p,wen1_p,cen1_n,wen1_n;    // ram1 select  and write
  reg cen2_p,wen2_p,cen2_n,wen2_n;    // ram2 select  and  write
  reg w2_done_n,  w1_done_n;  // ram writen  is over 
  reg calc_done_n;   // All of  64 data's  output is over 
  reg d_en_n;           // one data has caculated
  reg [15:0] mul; 
  reg [18:0] mul_reg;
  reg [2:0] count_i, count_j, count_k, count_mul;  
  wire [5:0] addr_1, addr_2;
  
   always @(posedge clk )  begin
        if(!rst_b) begin
             st_p <= NOP;
        end  else  begin
             st_p <= st_n; 
        end
   end
  
   always @(posedge clk) begin
       if (!rst_b)  begin
             cen1_p  <= 1'b1;  wen1_p  <= 1'b0;    // control signal  for  RAM1
             cen2_p  <= 1'b1;  wen2_p  <= 1'b0;   // control signal  for  RAM2
             w1_done <= 1'b0;     // RAM1  have not be writen
             w2_done <= 1'b0;     // RAM1  have not be writen
             calc_done <= 1'b0;    // caculate has not over
             cnt1_p <= 6'b000000;   // counter1 
             cnt2_p <= 6'b000000;   // counter2
       end else begin
             cen1_p  <= cen1_n;  wen1_p  <= wen1_n;   
             cen2_p  <= cen2_n;  wen2_p  <= wen2_n;   
             w1_done  <= w1_done_n;     
             w2_done  <= w2_done_n;     
             calc_done  <= calc_done_n;   
             cnt1_p <= cnt1_n;
             cnt2_p <= cnt2_n;  
       end
   end

   always @(st_p or start or cnt1_p )  begin   //synopsys full_case parallel_case
       st_n = NOP;
       mul = 16'b0;
       cen1_n  = 1'b1;  wen1_n  = 1'b0;    // control signal  for  RAM1
       cen2_n  = 1'b1;  wen2_n  = 1'b0;   // control signal  for  RAM2
       w1_done_n = 1'b0;     // RAM1  have not be writen
       w2_done_n = 1'b0;     // RAM2  have not be writen
       calc_done_n = 1'b0;    // caculate has not over
       cnt1_n = 6'b000000;  cnt2_n = 6'b000000;
       case (st_p) 
            2'b00:  begin
                if( start==IN_1 )  begin
                      st_n = IN_1;
                end  else  if( start==IN_2 )  begin
                      st_n = IN_2;
                end  else  if( start==CALC )  begin
                      st_n = CALC;
                end else begin
                      st_n = NOP; 
                end
            end
            2'b01:  begin
                 if( cnt1_n==6'd63 ) begin   // reture to NOP
                      w1_done_n = 1'b1;    // RAM1  have be writen
                 end else begin
                      st_n = IN_1;
                      cnt1_n = cnt1_p + 1'b1;
                      cen1_n  = 1'b0;    // select RAM1
                       
                      
                 end
            end
            2'b10:  begin
                 if(cnt2_p==6'd63) begin   // reture to NOP
                      w2_done_n = 1'b1;    // RAM2  have be writen
                 end else begin
                      st_n = IN_2;
                      cen2_n  = 1'b0;    // select RAM1
                      if(d_rdy==1'b1)  begin
                          cnt2_n = cnt2_p + 1'b1;
                      end else begin
                          cnt2_n = cnt2_p;
                      end
                 end
            end
            2'b11:  begin
                if ( (cnt2_p==6'd63) & (cnt1_p==6'd63 ) )  begin   // reture to NOP
                      calc_done_n = 1'b1;    // RAM2  have be writen
                 end else begin
                      st_n = CALC;
                      cen1_n  = 1'b0;    // select RAM1
                      cen2_n  = 1'b0;    // select RAM2
                      wen1_n  = 1'b1;    // read RAM2
                      wen2_n  = 1'b1;    // read RAM2
                 end
                mul = q_1 * q_2; 
                 
            end
       endcase
   end
  
  assign   d_out = mul;
  assign  addr_1 = cnt1_p; 
  assign  addr_2 = cnt2_p;
 
  sram_64X8	u01_sram_64X8 (.Q(q_1),.CLK(clk),.CEN(cen1_p),.WEN(wen1_p),.A(addr_1),.D({2'b00,addr_1}),.OEN(1'b0));
  sram_64X8	u02_sram_64X8 (.Q(q_2),.CLK(clk),.CEN(cen2_p),.WEN(wen2_p),.A(addr_2),.D(d_in),.OEN(1'b0));

 endmodule