dct.sss

arm7内核的verilog代码

/module sram_rw(clk,
							 rst_b,
							 cmd,
							 w_done,
							 r_done,
							 q
							 );
input clk, rst_b;
input [1:0] cmd;
wire [1:0] cmd;

output w_done, r_done;
reg w_done, r_done;
output [7:0] q;
wire [7:0] q;

parameter IDLE=2'b00,
					WRITE=2'b01,
					READ=2'b10;

reg [1:0] st_p,st_n;
reg [5:0]	cnt_p, cnt_n;
reg w_done_n, r_done_n;
reg cen_p,wen_p,cen_n,wen_n;

always @(st_p or cmd or cnt_p) begin	//next state
	w_done_n=1'b0;
	r_done_n=1'b0;
	st_n=IDLE;
	cnt_n=6'b0;
	cen_n=1'b1;
	wen_n=1'b0;	
	case(st_p)	//synopsys full_case parallel_case
		2'b00: begin
			if(cmd==WRITE) begin
				st_n=WRITE;
				cnt_n=6'b0;
				cen_n=1'b0;
				wen_n=1'b0;
			end else if(cmd==READ) begin
				st_n=READ;
				cnt_n=6'b0;
				cen_n=1'b0;
				wen_n=1'b1;				
			end else begin	//IDLE
				st_n=IDLE;			
			end
		end
		2'b01: begin
			if(cnt1_p==6'd63) begin	//IDLE
				w1_done_n = 1'b1;				
			end else begin
				st_n=IN_1;
				cnt1_n = cnt1_p + 1'b1;
				cen1_n = 1'b0;
				wen1_n = 1'b0;			
			end
		end
		2'b10: begin
			if(cnt2_p==6'd63) begin	//IDLE
				w2_done_n = 1'b1;
			end else begin
				st_n=IN_2;
				cnt2_n=cnt2_p+1'b1;
				cen2_n=1'b0;
				wen2_n=1'b1;			
			end		
		end
	  endcase
     end

     always @(posedge clk) begin //state update
	if(!rst_b) begin
		st_p<=NOP;
	end else begin
		st_p<=st_n;
	end
     end

     always @(posedge clk) begin //state machine output
	   if(!rst_b) begin
		cnt1_p <=6'b000000;
		w1_done <=1'b0;
		w2_done <=1'b0;
		cen1_p  <= 1'b1;
		wen1_p <= 1'b0;			
	   end else begin
		cnt1_p <=cnt1_n;
		w1_done <= w1_done_n;
		w2_done <= w2_done_n;
		cen1_p <= cen1_n;
		wen1_p <= wen1_n;		
	  end
     end

     wire   [5:0] addr_1, addr_2;
    
     assign addr=cnt_p;
     assign din=cnt_p+1'b1;
     sram_64X8	 u1_sram_64X8(.Q(q_1),.CLK(clk),.CEN(cen1_p),.WEN(wen1_p),.A(addr_1),.D(d_in),.OEN(1'b0));
     

endmodule