mobile_sdram.map.qmsg

cpld 控制 8-32M sdram 控制器 maxII epm570实现。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 04 10:53:25 2008 " "Info: Processing started: Mon Aug 04 10:53:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mobile_sdram -c mobile_sdram " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mobile_sdram -c mobile_sdram" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addr_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file addr_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 addr_gen " "Info: Found entity 1: addr_gen" {  } { { "addr_gen.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mobile_sdram.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mobile_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 mobile_sdram " "Info: Found entity 1: mobile_sdram" {  } { { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "upcount_2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file upcount_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 upcount_2 " "Info: Found entity 1: upcount_2" {  } { { "upcount_2.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/upcount_2.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "upcount_4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file upcount_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 upcount_4 " "Info: Found entity 1: upcount_4" {  } { { "upcount_4.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/upcount_4.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mobile_sdram " "Info: Elaborating entity \"mobile_sdram\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addr_gen addr_gen:address " "Info: Elaborating entity \"addr_gen\" for hierarchy \"addr_gen:address\"" {  } { { "mobile_sdram.v" "address" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 52 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "lemr_st addr_gen.v(18) " "Warning (10036): Verilog HDL or VHDL warning at addr_gen.v(18): object \"lemr_st\" assigned a value but never read" {  } { { "addr_gen.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v" 18 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "upcount_2 upcount_2:cas_cntr " "Info: Elaborating entity \"upcount_2\" for hierarchy \"upcount_2:cas_cntr\"" {  } { { "mobile_sdram.v" "cas_cntr" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "upcount_4 upcount_4:read_cntr " "Info: Elaborating entity \"upcount_4\" for hierarchy \"upcount_4:read_cntr\"" {  } { { "mobile_sdram.v" "read_cntr" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 55 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "ldqm GND " "Warning: Pin \"ldqm\" stuck at GND" {  } { { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 28 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "udqm GND " "Warning: Pin \"udqm\" stuck at GND" {  } { { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 28 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 28 -1 0 } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 28 -1 0 } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 28 -1 0 } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 28 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "231 " "Info: Implemented 231 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "30 " "Info: Implemented 30 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "23 " "Info: Implemented 23 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "32 " "Info: Implemented 32 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "146 " "Info: Implemented 146 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 04 10:53:30 2008 " "Info: Processing ended: Mon Aug 04 10:53:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}