mobile_sdram.tan.qmsg

cpld 控制 8-32M sdram 控制器 maxII epm570实现。

{ "Info" "ITDB_TH_RESULT" "addr_gen:address\|a\[6\] addr\[6\] clk -0.684 ns register " "Info: th for register \"addr_gen:address\|a\[6\]\" (data pin = \"addr\[6\]\", clock pin = \"clk\") is -0.684 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.302 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_18 59 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 59; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.574 ns) 2.302 ns addr_gen:address\|a\[6\] 2 REG LC_X5_Y4_N5 1 " "Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.302 ns; Loc. = LC_X5_Y4_N5; Fanout = 1; REG Node = 'addr_gen:address\|a\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.575 ns" { clk addr_gen:address|a[6] } "NODE_NAME" } } { "addr_gen.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 56.52 % ) " "Info: Total cell delay = 1.301 ns ( 56.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.001 ns ( 43.48 % ) " "Info: Total interconnect delay = 1.001 ns ( 43.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk addr_gen:address|a[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout addr_gen:address|a[6] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.138 ns + " "Info: + Micro hold delay of destination is 0.138 ns" {  } { { "addr_gen.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v" 35 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.124 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns addr\[6\] 1 PIN PIN_37 1 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_37; Fanout = 1; PIN Node = 'addr\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { addr[6] } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.677 ns) + CELL(0.739 ns) 3.124 ns addr_gen:address\|a\[6\] 2 REG LC_X5_Y4_N5 1 " "Info: 2: + IC(1.677 ns) + CELL(0.739 ns) = 3.124 ns; Loc. = LC_X5_Y4_N5; Fanout = 1; REG Node = 'addr_gen:address\|a\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.416 ns" { addr[6] addr_gen:address|a[6] } "NODE_NAME" } } { "addr_gen.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.447 ns ( 46.32 % ) " "Info: Total cell delay = 1.447 ns ( 46.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.677 ns ( 53.68 % ) " "Info: Total interconnect delay = 1.677 ns ( 53.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.124 ns" { addr[6] addr_gen:address|a[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.124 ns" { addr[6] addr[6]~combout addr_gen:address|a[6] } { 0.000ns 0.000ns 1.677ns } { 0.000ns 0.708ns 0.739ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk addr_gen:address|a[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout addr_gen:address|a[6] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.124 ns" { addr[6] addr_gen:address|a[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.124 ns" { addr[6] addr[6]~combout addr_gen:address|a[6] } { 0.000ns 0.000ns 1.677ns } { 0.000ns 0.708ns 0.739ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 04 10:53:46 2008 " "Info: Processing ended: Mon Aug 04 10:53:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}