mobile_sdram.tan.qmsg

cpld 控制 8-32M sdram 控制器 maxII epm570实现。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register upcount_4:read_cntr\|count\[3\] register nxt_state\[3\] 128.45 MHz 7.785 ns Internal " "Info: Clock \"clk\" has Internal fmax of 128.45 MHz between source register \"upcount_4:read_cntr\|count\[3\]\" and destination register \"nxt_state\[3\]\" (period= 7.785 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.342 ns + Longest register register " "Info: + Longest register to register delay is 7.342 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns upcount_4:read_cntr\|count\[3\] 1 REG LC_X9_Y6_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N8; Fanout = 3; REG Node = 'upcount_4:read_cntr\|count\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { upcount_4:read_cntr|count[3] } "NODE_NAME" } } { "upcount_4.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/upcount_4.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.336 ns) + CELL(0.319 ns) 1.655 ns nxt_state~620 2 COMB LC_X9_Y6_N0 1 " "Info: 2: + IC(1.336 ns) + CELL(0.319 ns) = 1.655 ns; Loc. = LC_X9_Y6_N0; Fanout = 1; COMB Node = 'nxt_state~620'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.655 ns" { upcount_4:read_cntr|count[3] nxt_state~620 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.481 ns) + CELL(0.319 ns) 2.455 ns nxt_state~621 3 COMB LC_X9_Y6_N9 1 " "Info: 3: + IC(0.481 ns) + CELL(0.319 ns) = 2.455 ns; Loc. = LC_X9_Y6_N9; Fanout = 1; COMB Node = 'nxt_state~621'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { nxt_state~620 nxt_state~621 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.513 ns) + CELL(0.319 ns) 4.287 ns Selector8~636 4 COMB LC_X10_Y5_N9 5 " "Info: 4: + IC(1.513 ns) + CELL(0.319 ns) = 4.287 ns; Loc. = LC_X10_Y5_N9; Fanout = 5; COMB Node = 'Selector8~636'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.832 ns" { nxt_state~621 Selector8~636 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.781 ns) + CELL(0.319 ns) 5.387 ns Selector8~639 5 COMB LC_X11_Y5_N4 1 " "Info: 5: + IC(0.781 ns) + CELL(0.319 ns) = 5.387 ns; Loc. = LC_X11_Y5_N4; Fanout = 1; COMB Node = 'Selector8~639'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { Selector8~636 Selector8~639 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.334 ns) + CELL(0.125 ns) 5.846 ns Selector8~641 6 COMB LC_X11_Y5_N5 1 " "Info: 6: + IC(0.334 ns) + CELL(0.125 ns) = 5.846 ns; Loc. = LC_X11_Y5_N5; Fanout = 1; COMB Node = 'Selector8~641'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.459 ns" { Selector8~639 Selector8~641 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.127 ns) + CELL(0.369 ns) 7.342 ns nxt_state\[3\] 7 REG LC_X11_Y4_N1 4 " "Info: 7: + IC(1.127 ns) + CELL(0.369 ns) = 7.342 ns; Loc. = LC_X11_Y4_N1; Fanout = 4; REG Node = 'nxt_state\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.496 ns" { Selector8~641 nxt_state[3] } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.770 ns ( 24.11 % ) " "Info: Total cell delay = 1.770 ns ( 24.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.572 ns ( 75.89 % ) " "Info: Total interconnect delay = 5.572 ns ( 75.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.342 ns" { upcount_4:read_cntr|count[3] nxt_state~620 nxt_state~621 Selector8~636 Selector8~639 Selector8~641 nxt_state[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.342 ns" { upcount_4:read_cntr|count[3] nxt_state~620 nxt_state~621 Selector8~636 Selector8~639 Selector8~641 nxt_state[3] } { 0.000ns 1.336ns 0.481ns 1.513ns 0.781ns 0.334ns 1.127ns } { 0.000ns 0.319ns 0.319ns 0.319ns 0.319ns 0.125ns 0.369ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.302 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_18 59 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 59; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.574 ns) 2.302 ns nxt_state\[3\] 2 REG LC_X11_Y4_N1 4 " "Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.302 ns; Loc. = LC_X11_Y4_N1; Fanout = 4; REG Node = 'nxt_state\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.575 ns" { clk nxt_state[3] } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 56.52 % ) " "Info: Total cell delay = 1.301 ns ( 56.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.001 ns ( 43.48 % ) " "Info: Total interconnect delay = 1.001 ns ( 43.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk nxt_state[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout nxt_state[3] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.302 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_18 59 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 59; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.574 ns) 2.302 ns upcount_4:read_cntr\|count\[3\] 2 REG LC_X9_Y6_N8 3 " "Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.302 ns; Loc. = LC_X9_Y6_N8; Fanout = 3; REG Node = 'upcount_4:read_cntr\|count\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.575 ns" { clk upcount_4:read_cntr|count[3] } "NODE_NAME" } } { "upcount_4.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/upcount_4.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 56.52 % ) " "Info: Total cell delay = 1.301 ns ( 56.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.001 ns ( 43.48 % ) " "Info: Total interconnect delay = 1.001 ns ( 43.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk upcount_4:read_cntr|count[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout upcount_4:read_cntr|count[3] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk nxt_state[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout nxt_state[3] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk upcount_4:read_cntr|count[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout upcount_4:read_cntr|count[3] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "upcount_4.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/upcount_4.v" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 134 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.342 ns" { upcount_4:read_cntr|count[3] nxt_state~620 nxt_state~621 Selector8~636 Selector8~639 Selector8~641 nxt_state[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.342 ns" { upcount_4:read_cntr|count[3] nxt_state~620 nxt_state~621 Selector8~636 Selector8~639 Selector8~641 nxt_state[3] } { 0.000ns 1.336ns 0.481ns 1.513ns 0.781ns 0.334ns 1.127ns } { 0.000ns 0.319ns 0.319ns 0.319ns 0.319ns 0.125ns 0.369ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk nxt_state[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout nxt_state[3] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk upcount_4:read_cntr|count[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout upcount_4:read_cntr|count[3] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "nxt_state\[2\] cmd\[3\] clk 4.570 ns register " "Info: tsu for register \"nxt_state\[2\]\" (data pin = \"cmd\[3\]\", clock pin = \"clk\") is 4.570 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.664 ns + Longest pin register " "Info: + Longest pin to register delay is 6.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns cmd\[3\] 1 PIN PIN_103 9 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_103; Fanout = 9; PIN Node = 'cmd\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cmd[3] } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.580 ns) + CELL(0.462 ns) 2.750 ns Selector9~374 2 COMB LC_X12_Y4_N6 1 " "Info: 2: + IC(1.580 ns) + CELL(0.462 ns) = 2.750 ns; Loc. = LC_X12_Y4_N6; Fanout = 1; COMB Node = 'Selector9~374'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.042 ns" { cmd[3] Selector9~374 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.652 ns) + CELL(0.319 ns) 4.721 ns Selector9~375 3 COMB LC_X10_Y5_N1 1 " "Info: 3: + IC(1.652 ns) + CELL(0.319 ns) = 4.721 ns; Loc. = LC_X10_Y5_N1; Fanout = 1; COMB Node = 'Selector9~375'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.971 ns" { Selector9~374 Selector9~375 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.125 ns) 5.300 ns Selector9~376 4 COMB LC_X10_Y5_N0 1 " "Info: 4: + IC(0.454 ns) + CELL(0.125 ns) = 5.300 ns; Loc. = LC_X10_Y5_N0; Fanout = 1; COMB Node = 'Selector9~376'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.579 ns" { Selector9~375 Selector9~376 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.319 ns) 6.104 ns Selector9~378 5 COMB LC_X10_Y5_N3 1 " "Info: 5: + IC(0.485 ns) + CELL(0.319 ns) = 6.104 ns; Loc. = LC_X10_Y5_N3; Fanout = 1; COMB Node = 'Selector9~378'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.804 ns" { Selector9~376 Selector9~378 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.191 ns) + CELL(0.369 ns) 6.664 ns nxt_state\[2\] 6 REG LC_X10_Y5_N4 5 " "Info: 6: + IC(0.191 ns) + CELL(0.369 ns) = 6.664 ns; Loc. = LC_X10_Y5_N4; Fanout = 5; REG Node = 'nxt_state\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.560 ns" { Selector9~378 nxt_state[2] } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.302 ns ( 34.54 % ) " "Info: Total cell delay = 2.302 ns ( 34.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.362 ns ( 65.46 % ) " "Info: Total interconnect delay = 4.362 ns ( 65.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.664 ns" { cmd[3] Selector9~374 Selector9~375 Selector9~376 Selector9~378 nxt_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.664 ns" { cmd[3] cmd[3]~combout Selector9~374 Selector9~375 Selector9~376 Selector9~378 nxt_state[2] } { 0.000ns 0.000ns 1.580ns 1.652ns 0.454ns 0.485ns 0.191ns } { 0.000ns 0.708ns 0.462ns 0.319ns 0.125ns 0.319ns 0.369ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 134 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.302 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_18 59 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 59; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.574 ns) 2.302 ns nxt_state\[2\] 2 REG LC_X10_Y5_N4 5 " "Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.302 ns; Loc. = LC_X10_Y5_N4; Fanout = 5; REG Node = 'nxt_state\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.575 ns" { clk nxt_state[2] } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 56.52 % ) " "Info: Total cell delay = 1.301 ns ( 56.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.001 ns ( 43.48 % ) " "Info: Total interconnect delay = 1.001 ns ( 43.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk nxt_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout nxt_state[2] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.664 ns" { cmd[3] Selector9~374 Selector9~375 Selector9~376 Selector9~378 nxt_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.664 ns" { cmd[3] cmd[3]~combout Selector9~374 Selector9~375 Selector9~376 Selector9~378 nxt_state[2] } { 0.000ns 0.000ns 1.580ns 1.652ns 0.454ns 0.485ns 0.191ns } { 0.000ns 0.708ns 0.462ns 0.319ns 0.125ns 0.319ns 0.369ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk nxt_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout nxt_state[2] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk sd_a\[10\] addr_gen:address\|a\[10\] 5.394 ns register " "Info: tco from clock \"clk\" to destination pin \"sd_a\[10\]\" through register \"addr_gen:address\|a\[10\]\" is 5.394 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.302 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_18 59 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 59; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.574 ns) 2.302 ns addr_gen:address\|a\[10\] 2 REG LC_X5_Y4_N3 1 " "Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.302 ns; Loc. = LC_X5_Y4_N3; Fanout = 1; REG Node = 'addr_gen:address\|a\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.575 ns" { clk addr_gen:address|a[10] } "NODE_NAME" } } { "addr_gen.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 56.52 % ) " "Info: Total cell delay = 1.301 ns ( 56.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.001 ns ( 43.48 % ) " "Info: Total interconnect delay = 1.001 ns ( 43.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk addr_gen:address|a[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout addr_gen:address|a[10] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "addr_gen.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.857 ns + Longest register pin " "Info: + Longest register to pin delay is 2.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addr_gen:address\|a\[10\] 1 REG LC_X5_Y4_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N3; Fanout = 1; REG Node = 'addr_gen:address\|a\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { addr_gen:address|a[10] } "NODE_NAME" } } { "addr_gen.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/addr_gen.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.403 ns) + CELL(1.454 ns) 2.857 ns sd_a\[10\] 2 PIN PIN_137 0 " "Info: 2: + IC(1.403 ns) + CELL(1.454 ns) = 2.857 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'sd_a\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.857 ns" { addr_gen:address|a[10] sd_a[10] } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 50.89 % ) " "Info: Total cell delay = 1.454 ns ( 50.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.403 ns ( 49.11 % ) " "Info: Total interconnect delay = 1.403 ns ( 49.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.857 ns" { addr_gen:address|a[10] sd_a[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.857 ns" { addr_gen:address|a[10] sd_a[10] } { 0.000ns 1.403ns } { 0.000ns 1.454ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.302 ns" { clk addr_gen:address|a[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.302 ns" { clk clk~combout addr_gen:address|a[10] } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.857 ns" { addr_gen:address|a[10] sd_a[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.857 ns" { addr_gen:address|a[10] sd_a[10] } { 0.000ns 1.403ns } { 0.000ns 1.454ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "data\[15\] sd_data\[15\] 4.053 ns Longest " "Info: Longest tpd from source pin \"data\[15\]\" to destination pin \"sd_data\[15\]\" is 4.053 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data\[15\] 1 PIN PIN_118 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_118; Fanout = 1; PIN Node = 'data\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data[15] } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns data\[15\]~0 2 COMB IOC_X9_Y8_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = IOC_X9_Y8_N0; Fanout = 1; COMB Node = 'data\[15\]~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.708 ns" { data[15] data[15]~0 } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.891 ns) + CELL(1.454 ns) 4.053 ns sd_data\[15\] 3 PIN PIN_124 0 " "Info: 3: + IC(1.891 ns) + CELL(1.454 ns) = 4.053 ns; Loc. = PIN_124; Fanout = 0; PIN Node = 'sd_data\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.345 ns" { data[15]~0 sd_data[15] } "NODE_NAME" } } { "mobile_sdram.v" "" { Text "C:/Documents and Settings/wangkj/桌面/an499_design_example/Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example/quartus/mobile_sdram.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.162 ns ( 53.34 % ) " "Info: Total cell delay = 2.162 ns ( 53.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.891 ns ( 46.66 % ) " "Info: Total interconnect delay = 1.891 ns ( 46.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.053 ns" { data[15] data[15]~0 sd_data[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.053 ns" { data[15] data[15]~0 sd_data[15] } { 0.000ns 0.000ns 1.891ns } { 0.000ns 0.708ns 1.454ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}