_primary.vhd

来自「cpld 控制 8-32M sdram 控制器 maxII epm570实现。」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity addr_gen is
    generic(
        active_read_st  : integer := 1;
        read_st         : integer := 3;
        write_st        : integer := 4;
        lmr_st          : integer := 10;
        lemr_st         : integer := 14;
        active_write_st : integer := 16
    );
    port(
        clk             : in     vl_logic;
        addr            : in     vl_logic_vector(23 downto 0);
        pr_state        : in     vl_logic_vector(4 downto 0);
        ba              : out    vl_logic_vector(1 downto 0);
        a               : out    vl_logic_vector(12 downto 0)
    );
end addr_gen;