_primary.vhd

来自「cpld 控制 8-32M sdram 控制器 maxII epm570实现。」· VHDL 代码 · 共 53 行

library verilog;
use verilog.vl_types.all;
entity mobile_sdram is
    generic(
        inhibit         : integer := 12;
        read            : integer := 1;
        write           : integer := 2;
        power_down      : integer := 3;
        precharge       : integer := 4;
        refresh         : integer := 5;
        dpd             : integer := 6;
        lmr             : integer := 8;
        dpd_exit        : integer := 10;
        power_down_exit : integer := 11;
        nop             : integer := 0;
        idle_st         : integer := 0;
        active_read_st  : integer := 1;
        t_rcd_read_st   : integer := 2;
        read_st         : integer := 3;
        write_st        : integer := 4;
        cas_st          : integer := 5;
        read_data_st    : integer := 6;
        dpd_st          : integer := 7;
        refresh_st      : integer := 8;
        precharge_st    : integer := 9;
        lmr_st          : integer := 10;
        t_wr_st         : integer := 11;
        t_rp_st         : integer := 12;
        write_data_st   : integer := 13;
        power_down_st   : integer := 14;
        active_write_st : integer := 31;
        t_rcd_write_st  : integer := 16
    );
    port(
        sd_clk          : out    vl_logic;
        sd_cke          : out    vl_logic;
        sd_csn          : out    vl_logic;
        sd_casn         : out    vl_logic;
        sd_rasn         : out    vl_logic;
        sd_wen          : out    vl_logic;
        ldqm            : out    vl_logic;
        udqm            : out    vl_logic;
        sd_ba           : out    vl_logic_vector(1 downto 0);
        sd_a            : out    vl_logic_vector(12 downto 0);
        sd_data         : inout  vl_logic_vector(15 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        cmd             : in     vl_logic_vector(3 downto 0);
        data            : inout  vl_logic_vector(15 downto 0);
        addr            : in     vl_logic_vector(23 downto 0)
    );
end mobile_sdram;