_primary.vhd

来自「cpld 控制 8-32M sdram 控制器 maxII epm570实现。」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity upcount_4 is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        count_en        : in     vl_logic;
        count           : out    vl_logic_vector(3 downto 0)
    );
end upcount_4;