iir_filter_2.v

来自「FPGA数字AGC(帮同学做的毕业设计)」· Verilog 代码 · 共 49 行

module IIR_Filter_2(Data_out,Data_in,clock,reset);
//Second-order,Generic IIR Filter

parameter	order=2;
parameter	word_size_in=16;
parameter	word_size_out=2*word_size_in + 2;//??????//

parameter	b0=16'd7;		//Feedforward filter coefficients
parameter	b1=0;
parameter	b2=0;

parameter	a1=16'd46;		//Feedback filter coefficients
parameter	a2=16'd32;


output	[word_size_out-1:0] Data_out;
input	[word_size_in-1:0]	Data_in;
input	clock,reset;

reg	[word_size_in-1:0]	Samples_in[1:order];
reg	[word_size_in-1:0]	Samples_out[1:order];

wire	[word_size_out-1:0]	Data_feedforward;
wire	[word_size_out-1:0]	Data_feedback;

integer	k;

assign	Data_feedforward = b0*Data_in + b1*Samples_in[1] + b2*Samples_in[2];
assign	Data_feedback = a1*Samples_out[1]+a2*Samples_out[2];

assign	Data_out = Data_feedforward + Data_feedback;

always@(posedge clock)
	if(reset==1)
		for(k=1;k<order;k=k+1)
			begin
				Samples_in[k]<=0;
				Samples_out[k]<=0;
			end
	else begin
				Samples_in[1]  <= Data_in;
				Samples_out[1] <= Data_out;
		for(k=2;k<=order;k=k+1)
			begin
				Samples_in[k] <= Samples_in[k-1];
				Samples_out[k]<= Samples_out[k-1];
			end
	end
endmodule