cmpr_o0j.tdf

FPGA数字AGC(帮同学做的毕业设计)

--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=4 aclr aeb agb clock dataa datab CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ  VERSION_END


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--synthesis_resources = lut 15 
SUBDESIGN cmpr_o0j
( 
	aclr	:	input;
	aeb	:	output;
	agb	:	output;
	clock	:	input;
	dataa[3..0]	:	input;
	datab[3..0]	:	input;
) 
VARIABLE
	aeb_int	:	WIRE;
	agb_int	:	WIRE;
	aeb_dffe[0..0]	:	DFFE;
	agb_dffe[0..0]	:	DFFE;
BEGIN 
	IF (dataa[] == datab[]) THEN
		aeb_int = VCC;
	ELSE
		aeb_int = GND;
	END IF;
	IF (dataa[] > datab[]) THEN
		agb_int = VCC;
	ELSE
		agb_int = GND;
	END IF;
	aeb_dffe[0].d = aeb_int;
	aeb = aeb_dffe[0].q;
	agb_dffe[0].d = agb_int;
	agb = agb_dffe[0].q;
	aeb_dffe[].clrn = !aclr;
	aeb_dffe[].clk = clock;
	agb_dffe[].clrn = !aclr;
	agb_dffe[].clk = clock;
END;
--VALID FILE