d_agc.tan.qmsg

FPGA数字AGC(帮同学做的毕业设计)

{ "Info" "ITDB_TH_RESULT" "IIR_Filter_2:inst\|Samples_out\[1\]\[9\] reset_IIR sys_clock 3.226 ns register " "Info: th for register \"IIR_Filter_2:inst\|Samples_out\[1\]\[9\]\" (data pin = \"reset_IIR\", clock pin = \"sys_clock\") is 3.226 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 12.776 ns + Longest register " "Info: + Longest clock path from clock \"sys_clock\" to destination register is 12.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.309 ns) 1.309 ns sys_clock 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.309 ns) = 1.309 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'sys_clock'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clock } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 160 -352 -184 176 "sys_clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.909 ns) + CELL(0.995 ns) 3.213 ns inst3 2 REG LC_X1_Y35_N4 2 " "Info: 2: + IC(0.909 ns) + CELL(0.995 ns) = 3.213 ns; Loc. = LC_X1_Y35_N4; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "1.904 ns" { sys_clock inst3 } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 64 -112 -48 144 "inst3"