d_agc.tan.qmsg

FPGA数字AGC(帮同学做的毕业设计)

{ "Info" "ITDB_TSU_RESULT" "IIR_Filter_2:inst\|Samples_out\[2\]\[8\] reset_IIR sys_clock -1.628 ns register " "Info: tsu for register \"IIR_Filter_2:inst\|Samples_out\[2\]\[8\]\" (data pin = \"reset_IIR\", clock pin = \"sys_clock\") is -1.628 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.191 ns + Longest pin register " "Info: + Longest pin to register delay is 11.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.544 ns) 1.544 ns reset_IIR 1 PIN PIN_L11 32 " "Info: 1: + IC(0.000 ns) + CELL(1.544 ns) = 1.544 ns; Loc. = PIN_L11; Fanout = 32; PIN Node = 'reset_IIR'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset_IIR } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 184 392 560 200 "reset_IIR" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.665 ns) + CELL(0.982 ns) 11.191 ns IIR_Filter_2:inst\|Samples_out\[2\]\[8\] 2 REG LC_X59_Y50_N4 2 " "Info: 2: + IC(8.665 ns) + CELL(0.982 ns) = 11.191 ns; Loc. = LC_X59_Y50_N4; Fanout = 2; REG Node = 'IIR_Filter_2:inst\|Samples_out\[2\]\[8\]'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "9.647 ns" { reset_IIR IIR_Filter_2:inst|Samples_out[2][8] } "NODE_NAME" } } { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.526 ns ( 22.57 % ) " "Info: Total cell delay = 2.526 ns ( 22.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.665 ns ( 77.43 % ) " "Info: Total interconnect delay = 8.665 ns ( 77.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "11.191 ns" { reset_IIR IIR_Filter_2:inst|Samples_out[2][8] } "NODE_NAME" } } { "d:/software/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/software/quartus60/win/Technology_Viewer.qrui" "11.191 ns" { reset_IIR reset_IIR~out0 IIR_Filter_2:inst|Samples_out[2][8] } { 0.000ns 0.000ns 8.665ns } { 0.000ns 1.544ns 0.982ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.013 ns + " "Info: + Micro setup delay of destination is 0.013 ns" {  } { { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 12.832 ns - Shortest register " "Info: - Shortest clock path from clock \"sys_clock\" to destination register is 12.832 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.309 ns) 1.309 ns sys_clock 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.309 ns) = 1.309 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'sys_clock'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clock } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 160 -352 -184 176 "sys_clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.909 ns) + CELL(0.995 ns) 3.213 ns inst3 2 REG LC_X1_Y35_N4 2 " "Info: 2: + IC(0.909 ns) + CELL(0.995 ns) = 3.213 ns; Loc. = LC_X1_Y35_N4; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "1.904 ns" { sys_clock inst3 } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 64 -112 -48 144 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.586 ns) + CELL(0.995 ns) 4.794 ns inst2 3 REG LC_X1_Y35_N2 2 " "Info: 3: + IC(0.586 ns) + CELL(0.995 ns) = 4.794 ns; Loc. = LC_X1_Y35_N2; Fanout = 2; REG Node = 'inst2'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { inst3 inst2 } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 64 24 88 144 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.514 ns) + CELL(0.995 ns) 7.303 ns inst1 4 REG LC_X1_Y33_N2 33 " "Info: 4: + IC(1.514 ns) + CELL(0.995 ns) = 7.303 ns; Loc. = LC_X1_Y33_N2; Fanout = 33; REG Node = 'inst1'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "2.509 ns" { inst2 inst1 } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 64 160 224 144 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.772 ns) + CELL(0.757 ns) 12.832 ns IIR_Filter_2:inst\|Samples_out\[2\]\[8\] 5 REG LC_X59_Y50_N4 2 " "Info: 5: + IC(4.772 ns) + CELL(0.757 ns) = 12.832 ns; Loc. = LC_X59_Y50_N4; Fanout = 2; REG Node = 'IIR_Filter_2:inst\|Samples_out\[2\]\[8\]'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "5.529 ns" { inst1 IIR_Filter_2:inst|Samples_out[2][8] } "NODE_NAME" } } { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.051 ns ( 39.36 % ) " "Info: Total cell delay = 5.051 ns ( 39.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.781 ns ( 60.64 % ) " "Info: Total interconnect delay = 7.781 ns ( 60.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "12.832 ns" { sys_clock inst3 inst2 inst1 IIR_Filter_2:inst|Samples_out[2][8] } "NODE_NAME" } } { "d:/software/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/software/quartus60/win/Technology_Viewer.qrui" "12.832 ns" { sys_clock sys_clock~out0 inst3 inst2 inst1 IIR_Filter_2:inst|Samples_out[2][8] } { 0.000ns 0.000ns 0.909ns 0.586ns 1.514ns 4.772ns } { 0.000ns 1.309ns 0.995ns 0.995ns 0.995ns 0.757ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "11.191 ns" { reset_IIR IIR_Filter_2:inst|Samples_out[2][8] } "NODE_NAME" } } { "d:/software/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/software/quartus60/win/Technology_Viewer.qrui" "11.191 ns" { reset_IIR reset_IIR~out0 IIR_Filter_2:inst|Samples_out[2][8] } { 0.000ns 0.000ns 8.665ns } { 0.000ns 1.544ns 0.982ns } } } { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "12.832 ns" { sys_clock inst3 inst2 inst1 IIR_Filter_2:inst|Samples_out[2][8] } "NODE_NAME" } } { "d:/software/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/software/quartus60/win/Technology_Viewer.qrui" "12.832 ns" { sys_clock sys_clock~out0 inst3 inst2 inst1 IIR_Filter_2:inst|Samples_out[2][8] } { 0.000ns 0.000ns 0.909ns 0.586ns 1.514ns 4.772ns } { 0.000ns 1.309ns 0.995ns 0.995ns 0.995ns 0.757ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sys_clock filter_out\[19\] IIR_Filter_2:inst\|Samples_out\[1\]\[11\] 33.748 ns register " "Info: tco from clock \"sys_clock\" to destination pin \"filter_out\[19\]\" through register \"IIR_Filter_2:inst\|Samples_out\[1\]\[11\]\" is 33.748 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock source 12.828 ns + Longest register " "Info: + Longest clock path from clock \"sys_clock\" to source register is 12.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.309 ns) 1.309 ns sys_clock 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.309 ns) = 1.309 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'sys_clock'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clock } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 160 -352 -184 176 "sys_clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.909 ns) + CELL(0.995 ns) 3.213 ns inst3 2 REG LC_X1_Y35_N4 2 " "Info: 2: + IC(0.909 ns) + CELL(0.995 ns) = 3.213 ns; Loc. = LC_X1_Y35_N4; Fanout = 2; REG Node = 'inst3'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "1.904 ns" { sys_clock inst3 } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 64 -112 -48 144 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.586 ns) + CELL(0.995 ns) 4.794 ns inst2 3 REG LC_X1_Y35_N2 2 " "Info: 3: + IC(0.586 ns) + CELL(0.995 ns) = 4.794 ns; Loc. = LC_X1_Y35_N2; Fanout = 2; REG Node = 'inst2'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { inst3 inst2 } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 64 24 88 144 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.514 ns) + CELL(0.995 ns) 7.303 ns inst1 4 REG LC_X1_Y33_N2 33 " "Info: 4: + IC(1.514 ns) + CELL(0.995 ns) = 7.303 ns; Loc. = LC_X1_Y33_N2; Fanout = 33; REG Node = 'inst1'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "2.509 ns" { inst2 inst1 } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 64 160 224 144 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.768 ns) + CELL(0.757 ns) 12.828 ns IIR_Filter_2:inst\|Samples_out\[1\]\[11\] 5 REG LC_X59_Y48_N3 7 " "Info: 5: + IC(4.768 ns) + CELL(0.757 ns) = 12.828 ns; Loc. = LC_X59_Y48_N3; Fanout = 7; REG Node = 'IIR_Filter_2:inst\|Samples_out\[1\]\[11\]'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "5.525 ns" { inst1 IIR_Filter_2:inst|Samples_out[1][11] } "NODE_NAME" } } { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.051 ns ( 39.37 % ) " "Info: Total cell delay = 5.051 ns ( 39.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.777 ns ( 60.63 % ) " "Info: Total interconnect delay = 7.777 ns ( 60.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "12.828 ns" { sys_clock inst3 inst2 inst1 IIR_Filter_2:inst|Samples_out[1][11] } "NODE_NAME" } } { "d:/software/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/software/quartus60/win/Technology_Viewer.qrui" "12.828 ns" { sys_clock sys_clock~out0 inst3 inst2 inst1 IIR_Filter_2:inst|Samples_out[1][11] } { 0.000ns 0.000ns 0.909ns 0.586ns 1.514ns 4.768ns } { 0.000ns 1.309ns 0.995ns 0.995ns 0.995ns 0.757ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.238 ns + " "Info: + Micro clock to output delay of source is 0.238 ns" {  } { { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.682 ns + Longest register pin " "Info: + Longest register to pin delay is 20.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns IIR_Filter_2:inst\|Samples_out\[1\]\[11\] 1 REG LC_X59_Y48_N3 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X59_Y48_N3; Fanout = 7; REG Node = 'IIR_Filter_2:inst\|Samples_out\[1\]\[11\]'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "" { IIR_Filter_2:inst|Samples_out[1][11] } "NODE_NAME" } } { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.357 ns) + CELL(0.288 ns) 4.645 ns IIR_Filter_2:inst\|lpm_mult:Mult0\|multcore:mult_core\|romout\[2\]\[8\]~1605 2 COMB LC_X59_Y50_N2 3 " "Info: 2: + IC(4.357 ns) + CELL(0.288 ns) = 4.645 ns; Loc. = LC_X59_Y50_N2; Fanout = 3; COMB Node = 'IIR_Filter_2:inst\|lpm_mult:Mult0\|multcore:mult_core\|romout\[2\]\[8\]~1605'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "4.645 ns" { IIR_Filter_2:inst|Samples_out[1][11] IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|romout[2][8]~1605 } "NODE_NAME" } } { "multcore.tdf" "" { Text "d:/software/quartus60/libraries/megafunctions/multcore.tdf" 205 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.878 ns) + CELL(0.461 ns) 6.984 ns IIR_Filter_2:inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~85COUT1 3 COMB LC_X63_Y49_N3 2 " "Info: 3: + IC(1.878 ns) + CELL(0.461 ns) = 6.984 ns; Loc. = LC_X63_Y49_N3; Fanout = 2; COMB Node = 'IIR_Filter_2:inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~85COUT1'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "2.339 ns" { IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|romout[2][8]~1605 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~85COUT1 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/software/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.607 ns) 7.591 ns IIR_Filter_2:inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~82 4 COMB LC_X63_Y49_N4 3 " "Info: 4: + IC(0.000 ns) + CELL(0.607 ns) = 7.591 ns; Loc. = LC_X63_Y49_N4; Fanout = 3; COMB Node = 'IIR_Filter_2:inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~82'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "0.607 ns" { IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~85COUT1 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~82 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/software/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.398 ns) + CELL(0.621 ns) 9.610 ns IIR_Filter_2:inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~114 5 COMB LC_X62_Y48_N2 3 " "Info: 5: + IC(1.398 ns) + CELL(0.621 ns) = 9.610 ns; Loc. = LC_X62_Y48_N2; Fanout = 3; COMB Node = 'IIR_Filter_2:inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~114'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "2.019 ns" { IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~82 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~114 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/software/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.137 ns) + CELL(0.610 ns) 11.357 ns IIR_Filter_2:inst\|Data_feedback\[17\]~43COUT1_79 6 COMB LC_X61_Y48_N3 2 " "Info: 6: + IC(1.137 ns) + CELL(0.610 ns) = 11.357 ns; Loc. = LC_X61_Y48_N3; Fanout = 2; COMB Node = 'IIR_Filter_2:inst\|Data_feedback\[17\]~43COUT1_79'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "1.747 ns" { IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~114 IIR_Filter_2:inst|Data_feedback[17]~43COUT1_79 } "NODE_NAME" } } { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.607 ns) 11.964 ns IIR_Filter_2:inst\|Data_feedback\[18\]~40 7 COMB LC_X61_Y48_N4 3 " "Info: 7: + IC(0.000 ns) + CELL(0.607 ns) = 11.964 ns; Loc. = LC_X61_Y48_N4; Fanout = 3; COMB Node = 'IIR_Filter_2:inst\|Data_feedback\[18\]~40'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "0.607 ns" { IIR_Filter_2:inst|Data_feedback[17]~43COUT1_79 IIR_Filter_2:inst|Data_feedback[18]~40 } "NODE_NAME" } } { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.450 ns) + CELL(0.610 ns) 14.024 ns IIR_Filter_2:inst\|Add3~507COUT1_556 8 COMB LC_X60_Y47_N1 2 " "Info: 8: + IC(1.450 ns) + CELL(0.610 ns) = 14.024 ns; Loc. = LC_X60_Y47_N1; Fanout = 2; COMB Node = 'IIR_Filter_2:inst\|Add3~507COUT1_556'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "2.060 ns" { IIR_Filter_2:inst|Data_feedback[18]~40 IIR_Filter_2:inst|Add3~507COUT1_556 } "NODE_NAME" } } { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.607 ns) 14.631 ns IIR_Filter_2:inst\|Add3~504 9 COMB LC_X60_Y47_N2 1 " "Info: 9: + IC(0.000 ns) + CELL(0.607 ns) = 14.631 ns; Loc. = LC_X60_Y47_N2; Fanout = 1; COMB Node = 'IIR_Filter_2:inst\|Add3~504'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "0.607 ns" { IIR_Filter_2:inst|Add3~507COUT1_556 IIR_Filter_2:inst|Add3~504 } "NODE_NAME" } } { "IIR_Filter_2.v" "" { Text "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.547 ns) + CELL(2.504 ns) 20.682 ns filter_out\[19\] 10 PIN PIN_V11 0 " "Info: 10: + IC(3.547 ns) + CELL(2.504 ns) = 20.682 ns; Loc. = PIN_V11; Fanout = 0; PIN Node = 'filter_out\[19\]'" {  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "6.051 ns" { IIR_Filter_2:inst|Add3~504 filter_out[19] } "NODE_NAME" } } { "D_AGC.bdf" "" { Schematic "C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf" { { 80 944 1120 96 "filter_out\[33..0\]" "" } { 208 624 724 224 "filter_out\[33..30\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.915 ns ( 33.43 % ) " "Info: Total cell delay = 6.915 ns ( 33.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.767 ns ( 66.57 % ) " "Info: Total interconnect delay = 13.767 ns ( 66.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "20.682 ns" { IIR_Filter_2:inst|Samples_out[1][11] IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|romout[2][8]~1605 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~85COUT1 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~82 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~114 IIR_Filter_2:inst|Data_feedback[17]~43COUT1_79 IIR_Filter_2:inst|Data_feedback[18]~40 IIR_Filter_2:inst|Add3~507COUT1_556 IIR_Filter_2:inst|Add3~504 filter_out[19] } "NODE_NAME" } } { "d:/software/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/software/quartus60/win/Technology_Viewer.qrui" "20.682 ns" { IIR_Filter_2:inst|Samples_out[1][11] IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|romout[2][8]~1605 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~85COUT1 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~82 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~114 IIR_Filter_2:inst|Data_feedback[17]~43COUT1_79 IIR_Filter_2:inst|Data_feedback[18]~40 IIR_Filter_2:inst|Add3~507COUT1_556 IIR_Filter_2:inst|Add3~504 filter_out[19] } { 0.000ns 4.357ns 1.878ns 0.000ns 1.398ns 1.137ns 0.000ns 1.450ns 0.000ns 3.547ns } { 0.000ns 0.288ns 0.461ns 0.607ns 0.621ns 0.610ns 0.607ns 0.610ns 0.607ns 2.504ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "12.828 ns" { sys_clock inst3 inst2 inst1 IIR_Filter_2:inst|Samples_out[1][11] } "NODE_NAME" } } { "d:/software/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/software/quartus60/win/Technology_Viewer.qrui" "12.828 ns" { sys_clock sys_clock~out0 inst3 inst2 inst1 IIR_Filter_2:inst|Samples_out[1][11] } { 0.000ns 0.000ns 0.909ns 0.586ns 1.514ns 4.768ns } { 0.000ns 1.309ns 0.995ns 0.995ns 0.995ns 0.757ns } } } { "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/software/quartus60/win/TimingClosureFloorplan.fld" "" "20.682 ns" { IIR_Filter_2:inst|Samples_out[1][11] IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|romout[2][8]~1605 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~85COUT1 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~82 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~114 IIR_Filter_2:inst|Data_feedback[17]~43COUT1_79 IIR_Filter_2:inst|Data_feedback[18]~40 IIR_Filter_2:inst|Add3~507COUT1_556 IIR_Filter_2:inst|Add3~504 filter_out[19] } "NODE_NAME" } } { "d:/software/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/software/quartus60/win/Technology_Viewer.qrui" "20.682 ns" { IIR_Filter_2:inst|Samples_out[1][11] IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|romout[2][8]~1605 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~85COUT1 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~82 IIR_Filter_2:inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~114 IIR_Filter_2:inst|Data_feedback[17]~43COUT1_79 IIR_Filter_2:inst|Data_feedback[18]~40 IIR_Filter_2:inst|Add3~507COUT1_556 IIR_Filter_2:inst|Add3~504 filter_out[19] } { 0.000ns 4.357ns 1.878ns 0.000ns 1.398ns 1.137ns 0.000ns 1.450ns 0.000ns 3.547ns } { 0.000ns 0.288ns 0.461ns 0.607ns 0.621ns 0.610ns 0.607ns 0.610ns 0.607ns 2.504ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}