d_agc.hier_info

FPGA数字AGC(帮同学做的毕业设计)

reset => Samples_out[2][7].ENA
reset => Samples_out[2][6].ENA
reset => Samples_out[2][5].ENA
reset => Samples_out[2][4].ENA
reset => Samples_out[2][3].ENA
reset => Samples_out[2][2].ENA
reset => Samples_out[2][1].ENA
reset => Samples_out[2][0].ENA


|D_AGC|lpm_mult0:inst7
dataa[0] => dataa[0]~7.IN1
dataa[1] => dataa[1]~6.IN1
dataa[2] => dataa[2]~5.IN1
dataa[3] => dataa[3]~4.IN1
dataa[4] => dataa[4]~3.IN1
dataa[5] => dataa[5]~2.IN1
dataa[6] => dataa[6]~1.IN1
dataa[7] => dataa[7]~0.IN1
result[0] <= altsquare:altsquare_component.result
result[1] <= altsquare:altsquare_component.result
result[2] <= altsquare:altsquare_component.result
result[3] <= altsquare:altsquare_component.result
result[4] <= altsquare:altsquare_component.result
result[5] <= altsquare:altsquare_component.result
result[6] <= altsquare:altsquare_component.result
result[7] <= altsquare:altsquare_component.result
result[8] <= altsquare:altsquare_component.result
result[9] <= altsquare:altsquare_component.result
result[10] <= altsquare:altsquare_component.result
result[11] <= altsquare:altsquare_component.result
result[12] <= altsquare:altsquare_component.result
result[13] <= altsquare:altsquare_component.result
result[14] <= altsquare:altsquare_component.result
result[15] <= altsquare:altsquare_component.result


|D_AGC|lpm_mult0:inst7|altsquare:altsquare_component
aclr => ~NO_FANOUT~
clock => ~NO_FANOUT~
data[0] => altsquare_msc:auto_generated.data[0]
data[1] => altsquare_msc:auto_generated.data[1]
data[2] => altsquare_msc:auto_generated.data[2]
data[3] => altsquare_msc:auto_generated.data[3]
data[4] => altsquare_msc:auto_generated.data[4]
data[5] => altsquare_msc:auto_generated.data[5]
data[6] => altsquare_msc:auto_generated.data[6]
data[7] => altsquare_msc:auto_generated.data[7]
ena => ~NO_FANOUT~
result[0] <= altsquare_msc:auto_generated.result[0]
result[1] <= altsquare_msc:auto_generated.result[1]
result[2] <= altsquare_msc:auto_generated.result[2]
result[3] <= altsquare_msc:auto_generated.result[3]
result[4] <= altsquare_msc:auto_generated.result[4]
result[5] <= altsquare_msc:auto_generated.result[5]
result[6] <= altsquare_msc:auto_generated.result[6]
result[7] <= altsquare_msc:auto_generated.result[7]
result[8] <= altsquare_msc:auto_generated.result[8]
result[9] <= altsquare_msc:auto_generated.result[9]
result[10] <= altsquare_msc:auto_generated.result[10]
result[11] <= altsquare_msc:auto_generated.result[11]
result[12] <= altsquare_msc:auto_generated.result[12]
result[13] <= altsquare_msc:auto_generated.result[13]
result[14] <= altsquare_msc:auto_generated.result[14]
result[15] <= altsquare_msc:auto_generated.result[15]


|D_AGC|lpm_mult0:inst7|altsquare:altsquare_component|altsquare_msc:auto_generated
aclr => ~NO_FANOUT~
clock => ~NO_FANOUT~
data[0] => result[0].DATAIN
data[0] => w119w[0].IN1
data[0] => w14w[0].IN1
data[0] => w18w[0].IN1
data[0] => w31w[0].IN1
data[0] => w47w[0].IN1
data[0] => w67w[0].IN1
data[0] => w91w[0].IN1
data[1] => w10w[0].IN0
data[1] => w123w[0].IN1
data[1] => w14w[0].IN0
data[1] => w27w[0].IN1
data[1] => w34w[0].IN1
data[1] => w51w[0].IN1
data[1] => w71w[0].IN1
data[1] => w95w[0].IN1
data[2] => w127w[0].IN1
data[2] => w18w[0].IN0
data[2] => w23w[0].IN0
data[2] => w27w[0].IN0
data[2] => w43w[0].IN1
data[2] => w54w[0].IN1
data[2] => w75w[0].IN1
data[2] => w99w[0].IN1
data[3] => w103w[0].IN1
data[3] => w131w[0].IN1
data[3] => w31w[0].IN0
data[3] => w34w[0].IN0
data[3] => w39w[0].IN0
data[3] => w43w[0].IN0
data[3] => w63w[0].IN1
data[3] => w78w[0].IN1
data[4] => w106w[0].IN1
data[4] => w135w[0].IN1
data[4] => w47w[0].IN0
data[4] => w51w[0].IN0
data[4] => w54w[0].IN0
data[4] => w59w[0].IN0
data[4] => w63w[0].IN0
data[4] => w87w[0].IN1
data[5] => w115w[0].IN1
data[5] => w138w[0].IN1
data[5] => w67w[0].IN0
data[5] => w71w[0].IN0
data[5] => w75w[0].IN0
data[5] => w78w[0].IN0
data[5] => w83w[0].IN0
data[5] => w87w[0].IN0
data[6] => w103w[0].IN0
data[6] => w106w[0].IN0
data[6] => w111w[0].IN0
data[6] => w115w[0].IN0
data[6] => w147w[0].IN1
data[6] => w91w[0].IN0
data[6] => w95w[0].IN0
data[6] => w99w[0].IN0
data[7] => w119w[0].IN0
data[7] => w123w[0].IN0
data[7] => w127w[0].IN0
data[7] => w131w[0].IN0
data[7] => w135w[0].IN0
data[7] => w138w[0].IN0
data[7] => w143w[0].IN0
data[7] => w147w[0].IN0
ena => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= <GND>
result[2] <= w10w[0].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= sft4a[0].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= sft4a[1].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= sft4a[2].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= sft4a[3].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= sft4a[4].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= sft4a[5].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= sft4a[6].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= sft4a[7].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= sft4a[8].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= sft4a[9].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= sft4a[10].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= sft4a[11].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= sft4a[12].DB_MAX_OUTPUT_PORT_TYPE


|D_AGC|lpm_constant0:inst16
result[0] <= lpm_constant:lpm_constant_component.result
result[1] <= lpm_constant:lpm_constant_component.result
result[2] <= lpm_constant:lpm_constant_component.result
result[3] <= lpm_constant:lpm_constant_component.result
result[4] <= lpm_constant:lpm_constant_component.result
result[5] <= lpm_constant:lpm_constant_component.result
result[6] <= lpm_constant:lpm_constant_component.result
result[7] <= lpm_constant:lpm_constant_component.result


|D_AGC|lpm_constant0:inst16|lpm_constant:lpm_constant_component
result[0] <= <GND>
result[1] <= <GND>
result[2] <= <GND>
result[3] <= <GND>
result[4] <= <GND>
result[5] <= <GND>
result[6] <= <VCC>
result[7] <= <GND>


|D_AGC|lpm_counter0:inst5
aclr => aclr~0.IN1
clock => clock~0.IN1
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q


|D_AGC|lpm_counter0:inst5|lpm_counter:lpm_counter_component
clock => cntr_5sh:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => cntr_5sh:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_5sh:auto_generated.q[0]
q[1] <= cntr_5sh:auto_generated.q[1]
q[2] <= cntr_5sh:auto_generated.q[2]
q[3] <= cntr_5sh:auto_generated.q[3]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|D_AGC|lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_5sh:auto_generated
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT