d_agc.hier_info

FPGA数字AGC(帮同学做的毕业设计)

|D_AGC
out_square <= inst15.DB_MAX_OUTPUT_PORT_TYPE
sys_clock => com:inst14.clock
sys_clock => inst3.CLK
sys_clock => lpm_counter0:inst5.clock
aclr => com:inst14.aclr
aclr => lpm_counter0:inst5.aclr
filter_out[0] <= IIR_Filter_2:inst.Data_out[0]
filter_out[1] <= IIR_Filter_2:inst.Data_out[1]
filter_out[2] <= IIR_Filter_2:inst.Data_out[2]
filter_out[3] <= IIR_Filter_2:inst.Data_out[3]
filter_out[4] <= IIR_Filter_2:inst.Data_out[4]
filter_out[5] <= IIR_Filter_2:inst.Data_out[5]
filter_out[6] <= IIR_Filter_2:inst.Data_out[6]
filter_out[7] <= IIR_Filter_2:inst.Data_out[7]
filter_out[8] <= IIR_Filter_2:inst.Data_out[8]
filter_out[9] <= IIR_Filter_2:inst.Data_out[9]
filter_out[10] <= IIR_Filter_2:inst.Data_out[10]
filter_out[11] <= IIR_Filter_2:inst.Data_out[11]
filter_out[12] <= IIR_Filter_2:inst.Data_out[12]
filter_out[13] <= IIR_Filter_2:inst.Data_out[13]
filter_out[14] <= IIR_Filter_2:inst.Data_out[14]
filter_out[15] <= IIR_Filter_2:inst.Data_out[15]
filter_out[16] <= IIR_Filter_2:inst.Data_out[16]
filter_out[17] <= IIR_Filter_2:inst.Data_out[17]
filter_out[18] <= IIR_Filter_2:inst.Data_out[18]
filter_out[19] <= IIR_Filter_2:inst.Data_out[19]
filter_out[20] <= IIR_Filter_2:inst.Data_out[20]
filter_out[21] <= IIR_Filter_2:inst.Data_out[21]
filter_out[22] <= IIR_Filter_2:inst.Data_out[22]
filter_out[23] <= IIR_Filter_2:inst.Data_out[23]
filter_out[24] <= IIR_Filter_2:inst.Data_out[24]
filter_out[25] <= IIR_Filter_2:inst.Data_out[25]
filter_out[26] <= IIR_Filter_2:inst.Data_out[26]
filter_out[27] <= IIR_Filter_2:inst.Data_out[27]
filter_out[28] <= IIR_Filter_2:inst.Data_out[28]
filter_out[29] <= IIR_Filter_2:inst.Data_out[29]
filter_out[30] <= IIR_Filter_2:inst.Data_out[30]
filter_out[31] <= IIR_Filter_2:inst.Data_out[31]
filter_out[32] <= IIR_Filter_2:inst.Data_out[32]
filter_out[33] <= IIR_Filter_2:inst.Data_out[33]
reset_IIR => IIR_Filter_2:inst.reset
out1[0] <= lpm_constant0:inst16.result[0]
out1[1] <= lpm_constant0:inst16.result[1]
out1[2] <= lpm_constant0:inst16.result[2]
out1[3] <= lpm_constant0:inst16.result[3]
out1[4] <= lpm_constant0:inst16.result[4]
out1[5] <= lpm_constant0:inst16.result[5]
out1[6] <= lpm_constant0:inst16.result[6]
out1[7] <= lpm_constant0:inst16.result[7]
out2[0] <= lpm_mult0:inst7.result[0]
out2[1] <= lpm_mult0:inst7.result[1]
out2[2] <= lpm_mult0:inst7.result[2]
out2[3] <= lpm_mult0:inst7.result[3]
out2[4] <= lpm_mult0:inst7.result[4]
out2[5] <= lpm_mult0:inst7.result[5]
out2[6] <= lpm_mult0:inst7.result[6]
out2[7] <= lpm_mult0:inst7.result[7]
out2[8] <= lpm_mult0:inst7.result[8]
out2[9] <= lpm_mult0:inst7.result[9]
out2[10] <= lpm_mult0:inst7.result[10]
out2[11] <= lpm_mult0:inst7.result[11]
out2[12] <= lpm_mult0:inst7.result[12]
out2[13] <= lpm_mult0:inst7.result[13]
out2[14] <= lpm_mult0:inst7.result[14]
out2[15] <= lpm_mult0:inst7.result[15]


|D_AGC|com:inst14
aclr => aclr~0.IN1
clock => clock~0.IN1
dataa[0] => dataa[0]~3.IN1
dataa[1] => dataa[1]~2.IN1
dataa[2] => dataa[2]~1.IN1
dataa[3] => dataa[3]~0.IN1
datab[0] => datab[0]~3.IN1
datab[1] => datab[1]~2.IN1
datab[2] => datab[2]~1.IN1
datab[3] => datab[3]~0.IN1
aeb <= lpm_compare:lpm_compare_component.aeb
agb <= lpm_compare:lpm_compare_component.agb


|D_AGC|com:inst14|lpm_compare:lpm_compare_component
dataa[0] => cmpr_o0j:auto_generated.dataa[0]
dataa[1] => cmpr_o0j:auto_generated.dataa[1]
dataa[2] => cmpr_o0j:auto_generated.dataa[2]
dataa[3] => cmpr_o0j:auto_generated.dataa[3]
datab[0] => cmpr_o0j:auto_generated.datab[0]
datab[1] => cmpr_o0j:auto_generated.datab[1]
datab[2] => cmpr_o0j:auto_generated.datab[2]
datab[3] => cmpr_o0j:auto_generated.datab[3]
clock => cmpr_o0j:auto_generated.clock
aclr => cmpr_o0j:auto_generated.aclr
clken => ~NO_FANOUT~
alb <= <GND>
aeb <= cmpr_o0j:auto_generated.aeb
agb <= cmpr_o0j:auto_generated.agb
aleb <= <GND>
aneb <= <GND>
ageb <= <GND>


|D_AGC|com:inst14|lpm_compare:lpm_compare_component|cmpr_o0j:auto_generated
aeb <= aeb_dffe[0].DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_dffe[0].DB_MAX_OUTPUT_PORT_TYPE
clock => aeb_dffe[0].CLK
clock => agb_dffe[0].CLK
dataa[0] => op_1.IN8
dataa[1] => op_1.IN6
dataa[2] => op_1.IN4
dataa[3] => op_1.IN2
datab[0] => op_1.IN7
datab[1] => op_1.IN5
datab[2] => op_1.IN3
datab[3] => op_1.IN1


|D_AGC|IIR_Filter_2:inst
Data_out[0] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[1] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[2] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[3] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[4] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[5] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[6] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[7] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[8] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[9] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[10] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[11] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[12] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[13] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[14] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[15] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[16] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[17] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[18] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[19] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[20] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[21] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[22] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[23] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[24] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[25] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[26] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[27] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[28] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[29] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[30] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[31] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[32] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_out[33] <= Add3.DB_MAX_OUTPUT_PORT_TYPE
Data_in[0] => Add1.IN62
Data_in[0] => Add0.IN35
Data_in[1] => Add1.IN61
Data_in[1] => Add0.IN34
Data_in[2] => Add1.IN60
Data_in[2] => Add0.IN33
Data_in[3] => Add1.IN59
Data_in[3] => Add0.IN32
Data_in[4] => Add1.IN58
Data_in[4] => Add0.IN31
Data_in[5] => Add1.IN57
Data_in[5] => Add0.IN30
Data_in[6] => Add1.IN56
Data_in[6] => Add0.IN29
Data_in[7] => Add1.IN55
Data_in[7] => Add0.IN28
Data_in[8] => Add1.IN54
Data_in[8] => Add0.IN27
Data_in[9] => Add1.IN53
Data_in[9] => Add0.IN26
Data_in[10] => Add1.IN52
Data_in[10] => Add0.IN25
Data_in[11] => Add1.IN51
Data_in[11] => Add0.IN24
Data_in[12] => Add1.IN50
Data_in[12] => Add0.IN23
Data_in[13] => Add1.IN49
Data_in[13] => Add0.IN22
Data_in[14] => Add1.IN48
Data_in[14] => Add0.IN21
Data_in[15] => Add1.IN47
Data_in[15] => Add0.IN20
clock => Samples_out[1][15].CLK
clock => Samples_out[1][14].CLK
clock => Samples_out[1][13].CLK
clock => Samples_out[1][12].CLK
clock => Samples_out[1][11].CLK
clock => Samples_out[1][10].CLK
clock => Samples_out[1][9].CLK
clock => Samples_out[1][8].CLK
clock => Samples_out[1][7].CLK
clock => Samples_out[1][6].CLK
clock => Samples_out[1][5].CLK
clock => Samples_out[1][4].CLK
clock => Samples_out[1][3].CLK
clock => Samples_out[1][2].CLK
clock => Samples_out[1][1].CLK
clock => Samples_out[1][0].CLK
clock => Samples_out[2][15].CLK
clock => Samples_out[2][14].CLK
clock => Samples_out[2][13].CLK
clock => Samples_out[2][12].CLK
clock => Samples_out[2][11].CLK
clock => Samples_out[2][10].CLK
clock => Samples_out[2][9].CLK
clock => Samples_out[2][8].CLK
clock => Samples_out[2][7].CLK
clock => Samples_out[2][6].CLK
clock => Samples_out[2][5].CLK
clock => Samples_out[2][4].CLK
clock => Samples_out[2][3].CLK
clock => Samples_out[2][2].CLK
clock => Samples_out[2][1].CLK
clock => Samples_out[2][0].CLK
reset => Samples_out~0.OUTPUTSELECT
reset => Samples_out~1.OUTPUTSELECT
reset => Samples_out~2.OUTPUTSELECT
reset => Samples_out~3.OUTPUTSELECT
reset => Samples_out~4.OUTPUTSELECT
reset => Samples_out~5.OUTPUTSELECT
reset => Samples_out~6.OUTPUTSELECT
reset => Samples_out~7.OUTPUTSELECT
reset => Samples_out~8.OUTPUTSELECT
reset => Samples_out~9.OUTPUTSELECT
reset => Samples_out~10.OUTPUTSELECT
reset => Samples_out~11.OUTPUTSELECT
reset => Samples_out~12.OUTPUTSELECT
reset => Samples_out~13.OUTPUTSELECT
reset => Samples_out~14.OUTPUTSELECT
reset => Samples_out~15.OUTPUTSELECT
reset => Samples_out[2][15].ENA
reset => Samples_out[2][14].ENA
reset => Samples_out[2][13].ENA
reset => Samples_out[2][12].ENA
reset => Samples_out[2][11].ENA
reset => Samples_out[2][10].ENA
reset => Samples_out[2][9].ENA
reset => Samples_out[2][8].ENA