📄 d_agc.map.rpt
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Analysis & Synthesis report for D_AGC
Tue Jun 03 11:49:25 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Parameter Settings for User Entity Instance: com:inst14|lpm_compare:lpm_compare_component
9. Parameter Settings for User Entity Instance: IIR_Filter_2:inst
10. Parameter Settings for User Entity Instance: lpm_mult0:inst7|altsquare:altsquare_component
11. Parameter Settings for User Entity Instance: lpm_constant0:inst16|lpm_constant:lpm_constant_component
12. Parameter Settings for User Entity Instance: lpm_counter0:inst5|lpm_counter:lpm_counter_component
13. Parameter Settings for Inferred Entity Instance: IIR_Filter_2:inst|lpm_mult:Mult0
14. lpm_mult Parameter Settings by Entity Instance
15. Analysis & Synthesis Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Jun 03 11:49:25 2008 ;
; Quartus II Version ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name ; D_AGC ;
; Top-level Entity Name ; D_AGC ;
; Family ; Stratix ;
; Total logic elements ; 35 ;
; Total pins ; 62 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; DSP block 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP1S40F780C8 ; ;
; Top-level entity name ; D_AGC ; D_AGC ;
; Family name ; Stratix ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; Maximum DSP Block Usage ; Unlimited ; Unlimited ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Stratix/Stratix GX ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M-RAM Memory Blocks ; Unlimited ; Unlimited ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------+
; IIR_Filter_2.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/IIR_Filter_2.v ;
; D_AGC.bdf ; yes ; User Block Diagram/Schematic File ; C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/D_AGC.bdf ;
; com.v ; yes ; Other ; C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/com.v ;
; lpm_compare.tdf ; yes ; Megafunction ; d:/software/quartus60/libraries/megafunctions/lpm_compare.tdf ;
; comptree.inc ; yes ; Other ; d:/software/quartus60/libraries/megafunctions/comptree.inc ;
; altshift.inc ; yes ; Other ; d:/software/quartus60/libraries/megafunctions/altshift.inc ;
; aglobal60.inc ; yes ; Other ; d:/software/quartus60/libraries/megafunctions/aglobal60.inc ;
; db/cmpr_o0j.tdf ; yes ; Auto-Generated Megafunction ; C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/db/cmpr_o0j.tdf ;
; lpm_mult0.v ; yes ; Other ; C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/lpm_mult0.v ;
; altsquare.tdf ; yes ; Megafunction ; d:/software/quartus60/libraries/megafunctions/altsquare.tdf ;
; db/altsquare_msc.tdf ; yes ; Auto-Generated Megafunction ; C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/db/altsquare_msc.tdf ;
; lpm_constant0.v ; yes ; Other ; C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/lpm_constant0.v ;
; lpm_constant.tdf ; yes ; Megafunction ; d:/software/quartus60/libraries/megafunctions/lpm_constant.tdf ;
; lpm_counter0.v ; yes ; Other ; C:/Documents and Settings/joe/桌面/梁言的毕设/D_AGC/lpm_counter0.v ;
; lpm_counter.tdf ; yes ; Megafunction ; d:/software/quartus60/libraries/megafunctions/lpm_counter.tdf ;
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