d_agc.tan.rpt

FPGA数字AGC(帮同学做的毕业设计)

; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; sys_clock       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'sys_clock'                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------+--------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                 ; To                                   ; From Clock ; To Clock  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------+--------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 80.43 MHz ( period = 12.433 ns )                    ; IIR_Filter_2:inst|Samples_out[1][3]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 12.123 ns               ;
; N/A                                     ; 80.51 MHz ( period = 12.421 ns )                    ; IIR_Filter_2:inst|Samples_out[1][5]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 12.111 ns               ;
; N/A                                     ; 80.68 MHz ( period = 12.394 ns )                    ; IIR_Filter_2:inst|Samples_out[1][11] ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 12.087 ns               ;
; N/A                                     ; 80.70 MHz ( period = 12.391 ns )                    ; IIR_Filter_2:inst|Samples_out[1][2]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 12.081 ns               ;
; N/A                                     ; 81.16 MHz ( period = 12.321 ns )                    ; IIR_Filter_2:inst|Samples_out[1][3]  ; IIR_Filter_2:inst|Samples_out[1][14] ; sys_clock  ; sys_clock ; None                        ; None                      ; 12.011 ns               ;
; N/A                                     ; 81.29 MHz ( period = 12.302 ns )                    ; IIR_Filter_2:inst|Samples_out[1][6]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.992 ns               ;
; N/A                                     ; 81.39 MHz ( period = 12.286 ns )                    ; IIR_Filter_2:inst|Samples_out[1][4]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.976 ns               ;
; N/A                                     ; 81.44 MHz ( period = 12.279 ns )                    ; IIR_Filter_2:inst|Samples_out[1][2]  ; IIR_Filter_2:inst|Samples_out[1][14] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.969 ns               ;
; N/A                                     ; 81.49 MHz ( period = 12.272 ns )                    ; IIR_Filter_2:inst|Samples_out[1][7]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.962 ns               ;
; N/A                                     ; 81.68 MHz ( period = 12.243 ns )                    ; IIR_Filter_2:inst|Samples_out[1][10] ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.936 ns               ;
; N/A                                     ; 82.06 MHz ( period = 12.186 ns )                    ; IIR_Filter_2:inst|Samples_out[1][5]  ; IIR_Filter_2:inst|Samples_out[1][14] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.876 ns               ;
; N/A                                     ; 82.14 MHz ( period = 12.174 ns )                    ; IIR_Filter_2:inst|Samples_out[1][4]  ; IIR_Filter_2:inst|Samples_out[1][14] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.864 ns               ;
; N/A                                     ; 82.24 MHz ( period = 12.160 ns )                    ; IIR_Filter_2:inst|Samples_out[1][7]  ; IIR_Filter_2:inst|Samples_out[1][14] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.850 ns               ;
; N/A                                     ; 82.43 MHz ( period = 12.132 ns )                    ; IIR_Filter_2:inst|Samples_out[1][9]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.877 ns               ;
; N/A                                     ; 82.90 MHz ( period = 12.063 ns )                    ; IIR_Filter_2:inst|Samples_out[1][6]  ; IIR_Filter_2:inst|Samples_out[1][14] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.753 ns               ;
; N/A                                     ; 83.52 MHz ( period = 11.973 ns )                    ; IIR_Filter_2:inst|Samples_out[1][1]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.663 ns               ;
; N/A                                     ; 83.56 MHz ( period = 11.967 ns )                    ; IIR_Filter_2:inst|Samples_out[1][8]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.656 ns               ;
; N/A                                     ; 83.63 MHz ( period = 11.957 ns )                    ; IIR_Filter_2:inst|Samples_out[1][3]  ; IIR_Filter_2:inst|Samples_out[1][13] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.703 ns               ;
; N/A                                     ; 83.87 MHz ( period = 11.923 ns )                    ; IIR_Filter_2:inst|Samples_out[1][0]  ; IIR_Filter_2:inst|Samples_out[1][15] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.613 ns               ;
; N/A                                     ; 83.93 MHz ( period = 11.915 ns )                    ; IIR_Filter_2:inst|Samples_out[1][2]  ; IIR_Filter_2:inst|Samples_out[1][13] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.661 ns               ;
; N/A                                     ; 84.31 MHz ( period = 11.861 ns )                    ; IIR_Filter_2:inst|Samples_out[1][1]  ; IIR_Filter_2:inst|Samples_out[1][14] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.551 ns               ;
; N/A                                     ; 84.59 MHz ( period = 11.822 ns )                    ; IIR_Filter_2:inst|Samples_out[1][5]  ; IIR_Filter_2:inst|Samples_out[1][13] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.568 ns               ;
; N/A                                     ; 84.67 MHz ( period = 11.811 ns )                    ; IIR_Filter_2:inst|Samples_out[1][0]  ; IIR_Filter_2:inst|Samples_out[1][14] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.501 ns               ;
; N/A                                     ; 84.67 MHz ( period = 11.810 ns )                    ; IIR_Filter_2:inst|Samples_out[1][4]  ; IIR_Filter_2:inst|Samples_out[1][13] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.556 ns               ;
; N/A                                     ; 84.77 MHz ( period = 11.796 ns )                    ; IIR_Filter_2:inst|Samples_out[1][7]  ; IIR_Filter_2:inst|Samples_out[1][13] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.542 ns               ;
; N/A                                     ; 85.40 MHz ( period = 11.709 ns )                    ; IIR_Filter_2:inst|Samples_out[1][3]  ; IIR_Filter_2:inst|Samples_out[1][12] ; sys_clock  ; sys_clock ; None                        ; None                      ; 11.455 ns               ;