rom.map.qmsg

我用VHDL写的正弦

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 03 13:29:00 2008 " "Info: Processing started: Wed Sep 03 13:29:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rom -c rom " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rom -c rom" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom-a " "Info: Found design unit 1: rom-a" {  } { { "rom.vhd" "" { Text "D:/rom/rom.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rom " "Info: Found entity 1: rom" {  } { { "rom.vhd" "" { Text "D:/rom/rom.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "rom " "Info: Elaborating entity \"rom\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "romexam.vhd 2 1 " "Warning: Using design file romexam.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 romexam-SYN " "Info: Found design unit 1: romexam-SYN" {  } { { "romexam.vhd" "" { Text "D:/rom/romexam.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 romexam " "Info: Found entity 1: romexam" {  } { { "romexam.vhd" "" { Text "D:/rom/romexam.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "romexam romexam:u1 " "Info: Elaborating entity \"romexam\" for hierarchy \"romexam:u1\"" {  } { { "rom.vhd" "u1" { Text "D:/rom/rom.vhd" 32 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram romexam:u1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"romexam:u1\|altsyncram:altsyncram_component\"" {  } { { "romexam.vhd" "altsyncram_component" { Text "D:/rom/romexam.vhd" 81 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_s731.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s731.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_s731 " "Info: Found entity 1: altsyncram_s731" {  } { { "db/altsyncram_s731.tdf" "" { Text "D:/rom/db/altsyncram_s731.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_s731 romexam:u1\|altsyncram:altsyncram_component\|altsyncram_s731:auto_generated " "Info: Elaborating entity \"altsyncram_s731\" for hierarchy \"romexam:u1\|altsyncram:altsyncram_component\|altsyncram_s731:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Error" "ESGN_NO_INCR_TAP_IN_REGULAR_SYNTH" "" "Error: Incremental instances created by tools that communicate with a device via the JTAG interface, such as SignalTap II Logic Analyzer, can only be supported when incremental compilation is set to Full incremental compilation" {  } {  } 0 0 "Incremental instances created by tools that communicate with a device via the JTAG interface, such as SignalTap II Logic Analyzer, can only be supported when incremental compilation is set to Full incremental compilation" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_BANNER_TIME" "Wed Sep 03 13:29:01 2008 " "Error: Processing ended: Wed Sep 03 13:29:01 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}