rom.map.rpt

我用VHDL写的正弦

+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                      ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; rom.vhd                          ; yes             ; User VHDL File               ; D:/rom/rom.vhd                                                    ;
; romexam.vhd                      ; yes             ; Other                        ; D:/rom/romexam.vhd                                                ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/lpm_decode.inc        ;
; aglobal51.inc                    ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/aglobal51.inc         ;
; altsyncram.inc                   ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/altsyncram.inc        ;
; a_rdenreg.inc                    ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Other                        ; d:/altera/quartus51/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_s731.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/rom/db/altsyncram_s731.tdf                                     ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------+
; Source assignments for romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------+
; Assignment                      ; Value              ; from ; to                                 ;
+---------------------------------+--------------------+------+------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                  ;
+---------------------------------+--------------------+------+------------------------------------+


+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: romexam:u1|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+----------------------------------+
; Parameter Name                     ; Value           ; Type                             ;
+------------------------------------+-----------------+----------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                          ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                       ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                     ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                   ;
; OPERATION_MODE                     ; ROM             ; Untyped                          ;
; WIDTH_A                            ; 8               ; Integer                          ;
; WIDTHAD_A                          ; 6               ; Integer                          ;
; NUMWORDS_A                         ; 64              ; Integer                          ;
; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                          ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                          ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                          ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                          ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                          ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                          ;
; WIDTH_B                            ; 1               ; Untyped                          ;
; WIDTHAD_B                          ; 1               ; Untyped                          ;
; NUMWORDS_B                         ; 1               ; Untyped                          ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                          ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                          ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                          ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                          ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                          ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                          ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                          ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                          ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                          ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                          ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                          ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                          ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                          ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                          ;
; BYTE_SIZE                          ; 8               ; Untyped                          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                          ;
; INIT_FILE                          ; ROM.HEX         ; Untyped                          ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                          ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                          ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                          ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                          ;
; CBXI_PARAMETER                     ; altsyncram_s731 ; Untyped                          ;
+------------------------------------+-----------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Sep 03 13:29:00 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rom -c rom
Info: Found 2 design units, including 1 entities, in source file rom.vhd
    Info: Found design unit 1: rom-a
    Info: Found entity 1: rom
Info: Elaborating entity "rom" for the top level hierarchy
Warning: Using design file romexam.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: romexam-SYN
    Info: Found entity 1: romexam
Info: Elaborating entity "romexam" for hierarchy "romexam:u1"
Info: Found 1 design units, including 1 entities, in source file ../altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "romexam:u1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s731.tdf
    Info: Found entity 1: altsyncram_s731
Info: Elaborating entity "altsyncram_s731" for hierarchy "romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated"
Error: Incremental instances created by tools that communicate with a device via the JTAG interface, such as SignalTap II Logic Analyzer, can only be supported when incremental compilation is set to Full incremental compilation
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 1 warning
    Error: Processing ended: Wed Sep 03 13:29:01 2008
    Error: Elapsed time: 00:00:01