rom_tb.vhd

我用VHDL写的正弦

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

USE ieee.std_logic_unsigned.ALL;
ENTITY rom_tb IS
END rom_tb;
ARCHITECTURE a OF rom_tb IS
component rom
port (
	  clk : in std_logic;
	 DOUT :	out std_logic_vector(7 downto 0)
		
);
end component;
signal clk : std_logic:='0';
signal dout  : std_logic_vector(7 downto 0) :="00000000";


begin
uut: rom port map
(
 clk=>clk,
dout=>dout

);
clk <= not clk after 10ns;

END a;