rom.tan.rpt

我用VHDL写的正弦

; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk                          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                        ; To                                                                                                                                                                                                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_datain_reg8                                                                            ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_datain_reg7                                                                            ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_datain_reg6                                                                            ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_datain_reg5                                                                            ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_datain_reg4                                                                            ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_datain_reg3                                                                            ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_datain_reg2                                                                            ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_datain_reg1                                                                            ; clk        ; clk      ; None                        ; None                      ; 6.292 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_address_reg8                                                                           ; clk        ; clk      ; None                        ; None                      ; 6.293 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_address_reg7                                                                           ; clk        ; clk      ; None                        ; None                      ; 6.293 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_address_reg6                                                                           ; clk        ; clk      ; None                        ; None                      ; 6.293 ns                ;
; N/A                                     ; 152.63 MHz ( period = 6.552 ns )                    ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0]                                       ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_address_reg5                                                                           ; clk        ; clk      ; None                        ; None                      ; 6.293 ns                ;