rom.tan.rpt

我用VHDL写的正弦

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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                  ; To                                                                                                                               ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 4.758 ns                         ; q1(0)                                                                                                                                                                 ; sld_signaltap:rom1|trigger_in_reg                                                                                                ; --                           ; clk                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 8.549 ns                         ; romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated|q_a[1]                                                                                      ; DOUT[1]                                                                                                                          ; clk                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 3.086 ns                         ; altera_internal_jtag~TDO                                                                                                                                              ; altera_reserved_tdo                                                                                                              ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; -0.061 ns                        ; altera_internal_jtag~TMSUTAP                                                                                                                                          ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14]                                                         ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 96.39 MHz ( period = 10.374 ns ) ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]                                                                                               ; sld_hub:sld_hub_inst|hub_tdo                                                                                                     ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 152.63 MHz ( period = 6.552 ns ) ; sld_signaltap:rom1|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_rmd:auto_generated|safe_q[0] ; sld_signaltap:rom1|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_faf2:auto_generated|ram_block1a3~porta_datain_reg0 ; clk                          ; clk                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                       ;                                                                                                                                  ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;