rom.map.eqn

我用VHDL写的正弦

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--JB1_q_a[0] is romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[0]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
JB1_q_a[0]_PORT_A_address_reg = DFFE(JB1_q_a[0]_PORT_A_address, JB1_q_a[0]_clock_0, , , );
JB1_q_a[0]_clock_0 = clk;
JB1_q_a[0]_PORT_A_data_out = MEMORY(, , JB1_q_a[0]_PORT_A_address_reg, , , , , , JB1_q_a[0]_clock_0, , , , , );
JB1_q_a[0]_PORT_A_data_out_reg = DFFE(JB1_q_a[0]_PORT_A_data_out, JB1_q_a[0]_clock_0, , , );
JB1_q_a[0] = JB1_q_a[0]_PORT_A_data_out_reg[0];


--JB1_q_a[1] is romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[1]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
JB1_q_a[1]_PORT_A_address_reg = DFFE(JB1_q_a[1]_PORT_A_address, JB1_q_a[1]_clock_0, , , );
JB1_q_a[1]_clock_0 = clk;
JB1_q_a[1]_PORT_A_data_out = MEMORY(, , JB1_q_a[1]_PORT_A_address_reg, , , , , , JB1_q_a[1]_clock_0, , , , , );
JB1_q_a[1]_PORT_A_data_out_reg = DFFE(JB1_q_a[1]_PORT_A_data_out, JB1_q_a[1]_clock_0, , , );
JB1_q_a[1] = JB1_q_a[1]_PORT_A_data_out_reg[0];


--JB1_q_a[2] is romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[2]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
JB1_q_a[2]_PORT_A_address_reg = DFFE(JB1_q_a[2]_PORT_A_address, JB1_q_a[2]_clock_0, , , );
JB1_q_a[2]_clock_0 = clk;
JB1_q_a[2]_PORT_A_data_out = MEMORY(, , JB1_q_a[2]_PORT_A_address_reg, , , , , , JB1_q_a[2]_clock_0, , , , , );
JB1_q_a[2]_PORT_A_data_out_reg = DFFE(JB1_q_a[2]_PORT_A_data_out, JB1_q_a[2]_clock_0, , , );
JB1_q_a[2] = JB1_q_a[2]_PORT_A_data_out_reg[0];


--JB1_q_a[3] is romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[3]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
JB1_q_a[3]_PORT_A_address_reg = DFFE(JB1_q_a[3]_PORT_A_address, JB1_q_a[3]_clock_0, , , );
JB1_q_a[3]_clock_0 = clk;
JB1_q_a[3]_PORT_A_data_out = MEMORY(, , JB1_q_a[3]_PORT_A_address_reg, , , , , , JB1_q_a[3]_clock_0, , , , , );
JB1_q_a[3]_PORT_A_data_out_reg = DFFE(JB1_q_a[3]_PORT_A_data_out, JB1_q_a[3]_clock_0, , , );
JB1_q_a[3] = JB1_q_a[3]_PORT_A_data_out_reg[0];


--JB1_q_a[4] is romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[4]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
JB1_q_a[4]_PORT_A_address_reg = DFFE(JB1_q_a[4]_PORT_A_address, JB1_q_a[4]_clock_0, , , );
JB1_q_a[4]_clock_0 = clk;
JB1_q_a[4]_PORT_A_data_out = MEMORY(, , JB1_q_a[4]_PORT_A_address_reg, , , , , , JB1_q_a[4]_clock_0, , , , , );
JB1_q_a[4]_PORT_A_data_out_reg = DFFE(JB1_q_a[4]_PORT_A_data_out, JB1_q_a[4]_clock_0, , , );
JB1_q_a[4] = JB1_q_a[4]_PORT_A_data_out_reg[0];


--JB1_q_a[5] is romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[5]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
JB1_q_a[5]_PORT_A_address_reg = DFFE(JB1_q_a[5]_PORT_A_address, JB1_q_a[5]_clock_0, , , );
JB1_q_a[5]_clock_0 = clk;
JB1_q_a[5]_PORT_A_data_out = MEMORY(, , JB1_q_a[5]_PORT_A_address_reg, , , , , , JB1_q_a[5]_clock_0, , , , , );
JB1_q_a[5]_PORT_A_data_out_reg = DFFE(JB1_q_a[5]_PORT_A_data_out, JB1_q_a[5]_clock_0, , , );
JB1_q_a[5] = JB1_q_a[5]_PORT_A_data_out_reg[0];


--JB1_q_a[6] is romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[6]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
JB1_q_a[6]_PORT_A_address_reg = DFFE(JB1_q_a[6]_PORT_A_address, JB1_q_a[6]_clock_0, , , );
JB1_q_a[6]_clock_0 = clk;
JB1_q_a[6]_PORT_A_data_out = MEMORY(, , JB1_q_a[6]_PORT_A_address_reg, , , , , , JB1_q_a[6]_clock_0, , , , , );
JB1_q_a[6]_PORT_A_data_out_reg = DFFE(JB1_q_a[6]_PORT_A_data_out, JB1_q_a[6]_clock_0, , , );
JB1_q_a[6] = JB1_q_a[6]_PORT_A_data_out_reg[0];


--JB1_q_a[7] is romexam:u1|altsyncram:altsyncram_component|altsyncram_s731:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[7]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
JB1_q_a[7]_PORT_A_address_reg = DFFE(JB1_q_a[7]_PORT_A_address, JB1_q_a[7]_clock_0, , , );
JB1_q_a[7]_clock_0 = clk;
JB1_q_a[7]_PORT_A_data_out = MEMORY(, , JB1_q_a[7]_PORT_A_address_reg, , , , , , JB1_q_a[7]_clock_0, , , , , );
JB1_q_a[7]_PORT_A_data_out_reg = DFFE(JB1_q_a[7]_PORT_A_data_out, JB1_q_a[7]_clock_0, , , );
JB1_q_a[7] = JB1_q_a[7]_PORT_A_data_out_reg[0];


--A1L6 is altera_internal_jtag~TDO
A1L6 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L18);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L18);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L18);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L18);


--q1[0] is q1[0]
q1[0] = DFFEAS(A1L29, clk,  ,  ,  ,  ,  , A1L25,  );


--q1[1] is q1[1]
q1[1] = DFFEAS(A1L32, clk,  ,  ,  ,  ,  , A1L25,  );


--q1[2] is q1[2]
q1[2] = DFFEAS(A1L35, clk,  ,  ,  ,  ,  , A1L25,  );


--q1[3] is q1[3]
q1[3] = DFFEAS(A1L38, clk,  ,  ,  ,  ,  , A1L25,  );


--q1[4] is q1[4]
q1[4] = DFFEAS(A1L41, clk,  ,  ,  ,  ,  , A1L25,  );


--q1[5] is q1[5]
q1[5] = DFFEAS(A1L44, clk,  ,  ,  ,  ,  , A1L25,  );


--C1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
C1_hub_tdo = AMPP_FUNCTION(!A1L5, C1L16, !GB1_state[8]);


--A1L29 is q1[0]~122
A1L29 = q1[0] $ VCC;

--A1L30 is q1[0]~123
A1L30 = CARRY(q1[0]);


--A1L24 is LessThan~76
A1L24 = !q1[3] # !q1[2] # !q1[1] # !q1[0];


--A1L25 is LessThan~77
A1L25 = !A1L24 & q1[4] & q1[5];


--A1L32 is q1[1]~124
A1L32 = q1[1] & !A1L30 # !q1[1] & (A1L30 # GND);

--A1L33 is q1[1]~125
A1L33 = CARRY(!A1L30 # !q1[1]);


--A1L35 is q1[2]~126
A1L35 = q1[2] & (A1L33 $ GND) # !q1[2] & !A1L33 & VCC;

--A1L36 is q1[2]~127
A1L36 = CARRY(q1[2] & !A1L33);


--A1L38 is q1[3]~128
A1L38 = q1[3] & !A1L36 # !q1[3] & (A1L36 # GND);

--A1L39 is q1[3]~129
A1L39 = CARRY(!A1L36 # !q1[3]);


--A1L41 is q1[4]~130
A1L41 = q1[4] & (A1L39 $ GND) # !q1[4] & !A1L39 & VCC;

--A1L42 is q1[4]~131
A1L42 = CARRY(q1[4] & !A1L39);


--A1L44 is q1[5]~132
A1L44 = q1[5] $ A1L42;


--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, A1L46, GB1_state[0], GB1_state[12]);


--EB3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]
EB3_Q[0] = AMPP_FUNCTION(A1L5, C1L28, C1_CLRN_SIGNAL, EB3L4);


--GB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
GB1_state[3] = AMPP_FUNCTION(A1L5, GB1L19);


--GB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
GB1_state[4] = AMPP_FUNCTION(A1L5, GB1L20, A1L7);


--GB1L21 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13
GB1L21 = AMPP_FUNCTION(GB1_state[3], GB1_state[4]);


--C1L10 is sld_hub:sld_hub_inst|hub_tdo~448
C1L10 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, EB3_Q[0], GB1L21, C1_hub_tdo);


--B1L33 is sld_signaltap:rom1|comb~37
B1L33 = AMPP_FUNCTION(GB1_state[3], GB1_state[4], C1_jtag_debug_mode_usr1);


--EB7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
EB7_Q[0] = AMPP_FUNCTION(A1L5, EB7L3, C1L24);


--G2_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]
G2_WORD_SR[0] = AMPP_FUNCTION(A1L5, G2L29, G2L22);


--C1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG
C1_HUB_BYPASS_REG = AMPP_FUNCTION(A1L5, C1L8);


--HB1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[0]
HB1_dffe1a[0] = AMPP_FUNCTION(A1L5, HB1_w_anode1w[3], C1_CLRN_SIGNAL, C1L4);


--C1L11 is sld_hub:sld_hub_inst|hub_tdo~449
C1L11 = AMPP_FUNCTION(G2_WORD_SR[0], C1_HUB_BYPASS_REG, HB1_dffe1a[0]);


--C1L12 is sld_hub:sld_hub_inst|hub_tdo~450
C1L12 = AMPP_FUNCTION(C1L10, B1L33, EB7_Q[0], C1L11);


--B1_bypass_reg_out is sld_signaltap:rom1|bypass_reg_out
B1_bypass_reg_out = AMPP_FUNCTION(A1L5, B1L32, !B1_reset_all);


--EB4_Q[5] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5]
EB4_Q[5] = AMPP_FUNCTION(A1L5, C1L23, C1_CLRN_SIGNAL, C1L27);


--EB4_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]
EB4_Q[3] = AMPP_FUNCTION(A1L5, C1L21, C1_CLRN_SIGNAL, C1L27);


--EB4_Q[4] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4]
EB4_Q[4] = AMPP_FUNCTION(A1L5, C1L22, C1_CLRN_SIGNAL, C1L27);


--C1L13 is sld_hub:sld_hub_inst|hub_tdo~451
C1L13 = AMPP_FUNCTION(B1_bypass_reg_out, EB4_Q[5], EB4_Q[3], EB4_Q[4]);


--L1_dffs[0] is sld_signaltap:rom1|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[0]
L1_dffs[0] = AMPP_FUNCTION(A1L5, L1_dffs[1], !B1_reset_all, H1_trigger_setup_ena);


--G1_WORD_SR[0] is sld_signaltap:rom1|sld_rom_sr:crc_rom_sr|WORD_SR[0]
G1_WORD_SR[0] = AMPP_FUNCTION(A1L5, G1L22, G1L18);