tb.v

128Mb DDR verilog源程序

        end
    endtask

    //write task supports burst lengths <= 16
    task write;
        input   [BA_BITS - 1 : 0] bank;
        input   [COL_BITS - 1 : 0] col;
        input                      ap; //Auto Precharge
        input [16*DM_BITS - 1 : 0] dm;
        input [16*DQ_BITS - 1 : 0] dq;
        reg    [ADDR_BITS - 1 : 0] atemp [1:0];
        reg      [DQ_BITS/DM_BITS - 1 : 0] dm_temp;
        integer i,j;
        begin
               cke     = 1'b1;
               cs_n    = 1'b0;
               ras_n   = 1'b1;
               cas_n   = 1'b0;
               we_n    = 1'b0;
               ba      =   bank;
               atemp[0] = col & 10'h3ff;   //ADDR[ 9: 0] = COL[ 9: 0]
               atemp[1] = (col>>10)<<11;   //ADDR[ N:11] = COL[ N:10]
               a = atemp[0] | atemp[1] | (ap<<10);
               
               for (i=0; i<=BL; i=i+1) begin
                	dqs_en <= #(WL*tck + i*tck/2) 1'b1;
                		if (i%2 === 0) begin
                    		dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b0}};
                		end else begin
                   			 dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b1}};
  	           end
  	              dq_en  <= #(WL*tck + i*tck/2 + tck/4) 1'b1;
                for (j=0; j<DM_BITS; j=j+1) begin
                    dm_temp = dm>>((i*DM_BITS + j)*DQ_BITS/DM_BITS);
                    dm_out[j] <= #(WL*tck + i*tck/2 + tck/4) &dm_temp;
                end
                dq_out <= #(WL*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
                case (i)
                    15: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[16*DM_BITS-1 : 15*DM_BITS];
                    14: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[15*DM_BITS-1 : 14*DM_BITS];
                    13: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[14*DM_BITS-1 : 13*DM_BITS];
                    12: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[13*DM_BITS-1 : 12*DM_BITS];
                    11: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[12*DM_BITS-1 : 11*DM_BITS];
                    10: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[11*DM_BITS-1 : 10*DM_BITS];
                     9: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[10*DM_BITS-1 :  9*DM_BITS];
                     8: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 9*DM_BITS-1 :  8*DM_BITS];
                     7: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 8*DM_BITS-1 :  7*DM_BITS];
                     6: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 7*DM_BITS-1 :  6*DM_BITS];
                     5: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 6*DM_BITS-1 :  5*DM_BITS];
                     4: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 5*DM_BITS-1 :  4*DM_BITS];
                     3: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 4*DM_BITS-1 :  3*DM_BITS];
                     2: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 3*DM_BITS-1 :  2*DM_BITS];
                     1: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 2*DM_BITS-1 :  1*DM_BITS];
                     0: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 1*DM_BITS-1 :  0*DM_BITS];
                endcase
                case (i)
                    15: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[16*DQ_BITS-1 : 15*DQ_BITS];
                    14: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[15*DQ_BITS-1 : 14*DQ_BITS];
                    13: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[14*DQ_BITS-1 : 13*DQ_BITS];
                    12: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[13*DQ_BITS-1 : 12*DQ_BITS];
                    11: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[12*DQ_BITS-1 : 11*DQ_BITS];
                    10: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[11*DQ_BITS-1 : 10*DQ_BITS];
                     9: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[10*DQ_BITS-1 :  9*DQ_BITS];
                     8: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 9*DQ_BITS-1 :  8*DQ_BITS];
                     7: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 8*DQ_BITS-1 :  7*DQ_BITS];
                     6: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 7*DQ_BITS-1 :  6*DQ_BITS];
                     5: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 6*DQ_BITS-1 :  5*DQ_BITS];
                     4: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 5*DQ_BITS-1 :  4*DQ_BITS];
                     3: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 4*DQ_BITS-1 :  3*DQ_BITS];
                     2: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 3*DQ_BITS-1 :  2*DQ_BITS];
                     1: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 2*DQ_BITS-1 :  1*DQ_BITS];
                     0: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 1*DQ_BITS-1 :  0*DQ_BITS];
                endcase
                dq_en  <= #(WL*tck + i*tck/2 + tck/4) 1'b1;
            end
            dqs_en <= #(WL*tck + BL*tck/2 + tck/2) 1'b0;
            dq_en  <= #(WL*tck + BL*tck/2 + tck/4) 1'b0;
            @(negedge clk);  
        end
    endtask

    task read;
        input   [BA_BITS - 1 : 0]bank;
        input   [COL_BITS - 1 : 0] col;
        input                      ap; //Auto Precharge
        reg    [ADDR_BITS - 1 : 0] atemp [1:0];
        begin
            cke     = 1'b1;
            cs_n    = 1'b0;
            ras_n   = 1'b1;
            cas_n   = 1'b0;
            we_n    = 1'b1;
            ba      =   bank;
            atemp[0] = col & 10'h3ff;   //ADDR[ 9: 0] = COL[ 9: 0]
            atemp[1] = (col>>10)<<11;   //ADDR[ N:11] = COL[ N:10]
            a = atemp[0] | atemp[1] | (ap<<10);
            @(negedge clk);
        end
    endtask

    // read with data verification
    task read_verify;
        input   [BA_BITS - 1 : 0] bank;
        input   [COL_BITS - 1 : 0] col;
        input                      ap; //Auto Precharge
        input [16*DM_BITS - 1 : 0] dm; //Expected Data Mask
        input [16*DQ_BITS - 1 : 0] dq; //Expected Data
        integer i;
        reg                  [2:0] brst_col;
        begin
            read (bank, col, ap);
            for (i=0; i<BL; i=i+1) begin
                // perform burst ordering
                brst_col = col ^ i;
                if (!BO) begin
                    brst_col = col + i;
                end
                if (BL == 4) begin
                    brst_col[2] = 1'b0 ;
                end else if (BL == 2) begin
                    brst_col[2:1] = 2'b00 ;
                end
                dm_fifo[2*RL + i] = dm >> (i*DM_BITS);
                dq_fifo[2*RL + i] = dq >> (i*DQ_BITS);
            end
        end
    endtask

    task nop;
        input  count;
        integer count;
        begin
            cke     =  1'b1;
            cs_n    =  1'b0;
            ras_n   =  1'b1;
            cas_n   =  1'b1;
            we_n    =  1'b1;
            repeat(count) @(negedge clk);
        end
    endtask

    task deselect;
        input  count;
        integer count;
        begin
            cke     =  1'b1;
            cs_n    =  1'b1;
            ras_n   =  1'b1;
            cas_n   =  1'b1;
            we_n    =  1'b1;
            repeat(count) @(negedge clk);
        end
    endtask

    task power_down;
        input  count;
        integer count;
        begin
            cke     =  1'b0;
            cs_n    =  1'b1;
            ras_n   =  1'b1;
            cas_n   =  1'b1;
            we_n    =  1'b1;
            repeat(count) @(negedge clk);
        end
    endtask

    function [16*DQ_BITS - 1 : 0] sort_data;
        input [16*DQ_BITS - 1 : 0] dq;
        input [2:0] col;
        integer i;
        reg   [2:0] brst_col;
        reg   [DQ_BITS - 1 :0] burst;
        begin
            sort_data = 0;
            for (i=0; i<BL; i=i+1) begin
                // perform burst ordering
                brst_col = col ^ i;
                if (!BO) begin
                    brst_col[1:0] = col + i;
                end
                burst = dq >> (brst_col*DQ_BITS);
                sort_data = sort_data | burst<<(i*DQ_BITS);
            end
        end
    endfunction

    // receiver(s) for data_verify process
    always @(dqs_in[0]) begin #(tDQSQ); dqs_receiver(0); end
    always @(dqs_in[1]) begin #(tDQSQ); dqs_receiver(1); end
    always @(dqs_in[2]) begin #(tDQSQ); dqs_receiver(2); end
    always @(dqs_in[3]) begin #(tDQSQ); dqs_receiver(3); end
    always @(dqs_in[4]) begin #(tDQSQ); dqs_receiver(4); end
    always @(dqs_in[5]) begin #(tDQSQ); dqs_receiver(5); end
    always @(dqs_in[6]) begin #(tDQSQ); dqs_receiver(6); end
    always @(dqs_in[7]) begin #(tDQSQ); dqs_receiver(7); end

    task dqs_receiver;
    input i;
    integer i;
    begin
        if (dqs_in[i]) begin
            case (i)
                0: dq_in_pos[ 7: 0] <= dq_in[ 7: 0];
                1: dq_in_pos[15: 8] <= dq_in[15: 8];
                2: dq_in_pos[23:16] <= dq_in[23:16];
                3: dq_in_pos[31:24] <= dq_in[31:24];
                4: dq_in_pos[39:32] <= dq_in[39:32];
                5: dq_in_pos[47:40] <= dq_in[47:40];
                6: dq_in_pos[55:48] <= dq_in[55:48];
                7: dq_in_pos[63:56] <= dq_in[63:56];
            endcase
        end else if (!dqs_in[i]) begin
            case (i)
                0: dq_in_neg[ 7: 0] <= dq_in[ 7: 0];
                1: dq_in_neg[15: 8] <= dq_in[15: 8];
                2: dq_in_neg[23:16] <= dq_in[23:16];
                3: dq_in_neg[31:24] <= dq_in[31:24];
                4: dq_in_pos[39:32] <= dq_in[39:32];
                5: dq_in_pos[47:40] <= dq_in[47:40];
                6: dq_in_pos[55:48] <= dq_in[55:48];
                7: dq_in_pos[63:56] <= dq_in[63:56];
            endcase
        end
    end
    endtask

     
    // perform data verification as a result of read_verify task call
    always @(clk) begin : data_verify
        integer i;
        reg [DM_BITS-1 : 0] data_mask;
        reg [8*DM_BITS-1 : 0] bit_mask;
        
        for (i=0; i<=14; i=i+1) begin
            dm_fifo[i] = dm_fifo[i+1];
            dq_fifo[i] = dq_fifo[i+1];
        end
        dm_fifo[13] = 'bz;
        dq_fifo[13] = 'bz;
//        dm_fifo[30] = 0;
//        dq_fifo[30] = 0;
        data_mask = dm_fifo[0];

        data_mask = dm_fifo[0];
       for (i=0; i<DM_BITS; i=i+1) begin
            bit_mask = {bit_mask, {8{~data_mask[i]}}};
       end
        if (clk) begin
            if ((dq_in_neg & bit_mask) != (dq_fifo[0] & bit_mask))
                $display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_neg, bit_mask);
        end else begin
            if ((dq_in_pos & bit_mask) != (dq_fifo[0] & bit_mask))
                $display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_pos, bit_mask);
        end
    end
 


    reg test_done;
	initial test_done = 0;

    // End-of-test triggered in 'subtest.vh'
    always @(test_done) begin : all_done
		if (test_done == 1) begin
      #5000
			$display ("Simulation is Complete");
			$stop(0);
			$finish;
		end
	end

	// Test included from external file
    `include "subtest.vh"
   
endmodule