📄 tb.v
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/****************************************************************************************
*
* File Name: tb.v
* Version: 5.7
* Model: BUS Functional
*
* Dependencies: ddr.v, ddr_parameters.v
*
* Description: Micron SDRAM DDR (Double Data Rate) test bench
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes* --------------------------------------------------------------------------------* 2.1 SPH 03/19/2002 - Second Release* - Fix tWR and several incompatability* between different simulators* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks.* - Added tDQSH and tDQSL timing checks.* 3.1 CAH 05/28/2003 - update all models to release version 3.1
* (no changes to this model)
* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3
* 3.3 JMK 09/11/2003 - Added initialization sequence checks.
* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v"
* - Fixed tWTR check
* 4.1 JMK 01/14/2001 - Grouped specify parameters by speed grade
* - Fixed mem_sizes parameter
* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module* - Changed Dq_buf size to [15:0]* 5.0 JMK 06/16/2004 - Added read to write checking.* - Added read with precharge truncation to write checking.* - Added associative memory array to reduce memory consumption.* - Added checking for required DQS edges during write.* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write.* - Fixed wdqs_valid window.* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored.* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.* - Added tRFC checking during Load Mode and Precharge.* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.* JMK 02/11/2005 - Changed the display format for numbers to hex.* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.* - Renamed parameters file with .vh extension.* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb
* - Added x32 functionality* 6.0 BAS 05/31/2007 - Added read_verify command****************************************************************************************/
`timescale 1ns / 1ps
module tb;
`include "ddr_parameters.vh"
reg clk ;
reg clk_n ;
reg cke ;
reg cs_n ;
reg ras_n ;
reg cas_n ;
reg we_n ;
reg [BA_BITS - 1 : 0] ba ;
reg [ADDR_BITS - 1 : 0] a ;
reg dq_en ; reg [DM_BITS - 1 : 0] dm_out ; reg [DQ_BITS - 1 : 0] dq_out ;
reg [DM_BITS-1 : 0] dm_fifo [0 : 13]; reg [DQ_BITS-1 : 0] dq_fifo [0 : 13]; reg [DQ_BITS-1 : 0] dq_in_pos ; reg [DQ_BITS-1 : 0] dq_in_neg ; reg dqs_en ; reg [DQS_BITS - 1 : 0] dqs_out ;
reg [12 : 0] mode_reg ; //Mode Register
reg [12 : 0] ext_mode_reg; //Extended Mode Register
wire BO = mode_reg[3]; //Burst Order wire [7 : 0] BL = (1<<mode_reg[2:0]); //Burst Length
wire [2 : 0] CL = (mode_reg[6:4] == 3'b110) ? 2.5 : mode_reg[6:4]; //CAS Latency wire dqs_n_en = ~ext_mode_reg[10]; //dqs# Enable wire [2 : 0] AL = ext_mode_reg[5:3]; //Additive Latency wire [3 : 0] RL = CL ; //Read Latency wire [3 : 0] WL = 1 ; //Write Latency
wire [DM_BITS - 1 : 0] dm = dq_en ? dm_out : {DM_BITS{1'bz}}; wire [DQ_BITS - 1 : 0] dq = dq_en ? dq_out : {DQ_BITS{1'bz}}; wire [DQS_BITS - 1 : 0] dqs = dqs_en ? dqs_out : {DQS_BITS{1'bz}}; wire [DQS_BITS - 1 : 0] dqs_n = (dqs_en & dqs_n_en) ? ~dqs_out : {DQS_BITS{1'bz}}; wire [DQS_BITS - 1 : 0] rdqs_n = {DM_BITS{1'bz}};
wire [15 : 0] dqs_in = dqs; wire [63 : 0] dq_in = dq; ddr sdramddr (
clk , clk_n , cke , cs_n , ras_n , cas_n , we_n , ba , a , dm , dq , dqs );
// timing definition in tCK units real tck ;
integer tmrd ; integer trap ; integer tras ; integer trc ; integer trfc ; integer trcd ; integer trp ; integer trrd ; integer twr ;
initial begin`ifdef period tck = `period ; `else tck = tCK;`endif tmrd = ciel(tMRD/tck); trap = ciel(tRAP/tck);
tras = ciel(tRAS/tck); trc = ciel(tRC/tck); trfc = ciel(tRFC/tck); trcd = ciel(tRCD/tck); trp = ciel(tRP/tck); trrd = ciel(tRRD/tck); twr = ciel(tWR/tck); end
initial clk <= 1'b1; initial clk_n <= 1'b0; always @(posedge clk) begin clk <= #(tck/2) 1'b0; clk_n <= #(tck/2) 1'b1; clk <= #(tck) 1'b1; clk_n <= #(tck) 1'b0; end function integer ciel; input number; real number; if (number > $rtoi(number)) ciel = $rtoi(number) + 1; else ciel = number; endfunction
task power_up;
begin
cke <= 1'b0; repeat(10) @(negedge clk);
$display ("%m at time %t TB: A 200 us delay is required before CKE can be brought high.", $time); @ (negedge clk) cke = 1'b1; nop (400/tck+1);
end
endtask
task load_mode;
input [BA_BITS - 1 : 0] bank;
input [ADDR_BITS - 1 : 0] addr;
begin
case (bank)
0: mode_reg = addr;
1: ext_mode_reg = addr;
endcase
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b0;
we_n = 1'b0;
ba = bank;
a = addr;
@(negedge clk);
end
endtask
task refresh;
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b0;
we_n = 1'b1;
@(negedge clk);
end
endtask
task burst_term; integer i;
begin cke = 1'b1; cs_n = 1'b0; ras_n = 1'b1; cas_n = 1'b1; we_n = 1'b0; @(negedge clk); for (i=0; i<BL; i=i+1) begin
dm_fifo[2*RL + i] = {DM_BITS{1'bz}} ;
dq_fifo[2*RL + i] = {DQ_BITS{1'bz}} ;
end
end endtask task self_refresh;
input count;
integer count;
begin
cke = 1'b0;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b0;
we_n = 1'b1;
repeat(count) @(negedge clk);
end
endtask
task precharge;
input [BA_BITS - 1 : 0] bank;
input ap; //precharge all
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b1;
we_n = 1'b0;
ba = bank;
a = (ap<<10);
@(negedge clk);
end
endtask
task activate;
input [BA_BITS - 1 : 0] bank;
input [ADDR_BITS - 1 : 0] row;
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b1;
we_n = 1'b1;
ba = bank;
a = row;
@(negedge clk);
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