wave_v.sdo

典型事例

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.


// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "WAVE")
  (DATE "02/22/2006 20:55:02")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 10 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE mclk\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (146.9:146.9:146.9) (146.9:146.9:146.9))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|add\~251_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (121.5:121.5:121.5) (126.7:126.7:126.7))
        (IOPATH dataa combout (59:59:59) (59:59:59))
        (IOPATH dataa cout (71.8:71.8:71.8) (71.8:71.8:71.8))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|count\[12\]\~1110_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (136.6:136.6:136.6) (138.3:138.3:138.3))
        (PORT datac (45.9:45.9:45.9) (47.8:47.8:47.8))
        (PORT datad (43.5:43.5:43.5) (44:44:44))
        (IOPATH dataa combout (59:59:59) (59:59:59))
        (IOPATH datac combout (29.2:29.2:29.2) (29.2:29.2:29.2))
        (IOPATH datad combout (11.4:11.4:11.4) (11.4:11.4:11.4))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|count\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (118.8:118.8:118.8) (123.5:123.5:123.5))
        (PORT datab (53.3:53.3:53.3) (53.7:53.7:53.7))
        (PORT datac (130.8:130.8:130.8) (135.6:135.6:135.6))
        (PORT datad (131.8:131.8:131.8) (131.2:131.2:131.2))
        (IOPATH dataa regin (73.8:73.8:73.8) (73.8:73.8:73.8))
        (IOPATH datab regin (60.7:60.7:60.7) (60.7:60.7:60.7))
        (IOPATH datac regin (47.8:47.8:47.8) (47.8:47.8:47.8))
        (IOPATH datad regin (30.9:30.9:30.9) (30.9:30.9:30.9))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|count\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (89.8:89.8:89.8) (89.8:89.8:89.8))
        (PORT clk (145.6:145.6:145.6) (143.4:143.4:143.4))
        (PORT ena (206.1:206.1:206.1) (215.5:215.5:215.5))
        (IOPATH (posedge clk) regout (22.4:22.4:22.4) (22.4:22.4:22.4))
        (IOPATH (posedge aclr) regout (28.3:28.3:28.3) (28.3:28.3:28.3))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (3.7:3.7:3.7))
      (SETUP ena (posedge clk) (3.7:3.7:3.7))
      (HOLD datain (posedge clk) (1.5:1.5:1.5))
      (HOLD ena (posedge clk) (1.5:1.5:1.5))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|add\~256_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (50.4:50.4:50.4) (51.5:51.5:51.5))
        (IOPATH datab combout (44.2:44.2:44.2) (44.2:44.2:44.2))
        (IOPATH cin combout (62.1:62.1:62.1) (62.1:62.1:62.1))
        (IOPATH datab cout0 (42.3:42.3:42.3) (42.3:42.3:42.3))
        (IOPATH datab cout1 (43.2:43.2:43.2) (43.2:43.2:43.2))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|count\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (131.7:131.7:131.7) (134.2:134.2:134.2))
        (PORT datab (135.9:135.9:135.9) (137.6:137.6:137.6))
        (PORT datac (78.3:78.3:78.3) (79.3:79.3:79.3))
        (PORT datad (42.7:42.7:42.7) (43.4:43.4:43.4))
        (IOPATH dataa regin (73.8:73.8:73.8) (73.8:73.8:73.8))
        (IOPATH datab regin (60.7:60.7:60.7) (60.7:60.7:60.7))
        (IOPATH datac regin (47.8:47.8:47.8) (47.8:47.8:47.8))
        (IOPATH datad regin (30.9:30.9:30.9) (30.9:30.9:30.9))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|count\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (89.8:89.8:89.8) (89.8:89.8:89.8))
        (PORT clk (145.6:145.6:145.6) (143.4:143.4:143.4))
        (PORT ena (154.3:154.3:154.3) (159.9:159.9:159.9))
        (IOPATH (posedge clk) regout (22.4:22.4:22.4) (22.4:22.4:22.4))
        (IOPATH (posedge aclr) regout (28.3:28.3:28.3) (28.3:28.3:28.3))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (3.7:3.7:3.7))
      (SETUP ena (posedge clk) (3.7:3.7:3.7))
      (HOLD datain (posedge clk) (1.5:1.5:1.5))
      (HOLD ena (posedge clk) (1.5:1.5:1.5))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|add\~211_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (52.3:52.3:52.3) (53.6:53.6:53.6))
        (IOPATH dataa combout (59:59:59) (59:59:59))
        (IOPATH cin combout (62.1:62.1:62.1) (62.1:62.1:62.1))
        (IOPATH cin0 combout (60.4:60.4:60.4) (60.4:60.4:60.4))
        (IOPATH cin1 combout (60.8:60.8:60.8) (60.8:60.8:60.8))
        (IOPATH dataa cout0 (56.4:56.4:56.4) (56.4:56.4:56.4))
        (IOPATH cin0 cout0 (7.8:7.8:7.8) (7.8:7.8:7.8))
        (IOPATH dataa cout1 (57.5:57.5:57.5) (57.5:57.5:57.5))
        (IOPATH cin1 cout1 (8:8:8) (8:8:8))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|count\[2\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (131.4:131.4:131.4) (134.3:134.3:134.3))
        (PORT datab (135.8:135.8:135.8) (137.4:137.4:137.4))
        (PORT datac (78.2:78.2:78.2) (79.1:79.1:79.1))
        (PORT datad (41.6:41.6:41.6) (42.5:42.5:42.5))
        (IOPATH dataa regin (73.8:73.8:73.8) (73.8:73.8:73.8))
        (IOPATH datab regin (60.7:60.7:60.7) (60.7:60.7:60.7))
        (IOPATH datac regin (47.8:47.8:47.8) (47.8:47.8:47.8))
        (IOPATH datad regin (30.9:30.9:30.9) (30.9:30.9:30.9))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|count\[2\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (89.8:89.8:89.8) (89.8:89.8:89.8))
        (PORT clk (145.6:145.6:145.6) (143.4:143.4:143.4))
        (PORT ena (154.3:154.3:154.3) (159.9:159.9:159.9))
        (IOPATH (posedge clk) regout (22.4:22.4:22.4) (22.4:22.4:22.4))
        (IOPATH (posedge aclr) regout (28.3:28.3:28.3) (28.3:28.3:28.3))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (3.7:3.7:3.7))
      (SETUP ena (posedge clk) (3.7:3.7:3.7))
      (HOLD datain (posedge clk) (1.5:1.5:1.5))
      (HOLD ena (posedge clk) (1.5:1.5:1.5))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|add\~216_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (50:50:50) (51.3:51.3:51.3))
        (IOPATH datab combout (44.2:44.2:44.2) (44.2:44.2:44.2))
        (IOPATH cin combout (62.1:62.1:62.1) (62.1:62.1:62.1))
        (IOPATH cin0 combout (60.4:60.4:60.4) (60.4:60.4:60.4))
        (IOPATH cin1 combout (60.8:60.8:60.8) (60.8:60.8:60.8))
        (IOPATH datab cout0 (42.3:42.3:42.3) (42.3:42.3:42.3))
        (IOPATH cin0 cout0 (7.8:7.8:7.8) (7.8:7.8:7.8))
        (IOPATH datab cout1 (43.2:43.2:43.2) (43.2:43.2:43.2))
        (IOPATH cin1 cout1 (8:8:8) (8:8:8))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|count\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (78.5:78.5:78.5) (77.5:77.5:77.5))
        (PORT datab (135.6:135.6:135.6) (137.3:137.3:137.3))
        (PORT datac (42.2:42.2:42.2) (45:45:45))
        (PORT datad (131.2:131.2:131.2) (133.4:133.4:133.4))
        (IOPATH dataa regin (73.8:73.8:73.8) (73.8:73.8:73.8))
        (IOPATH datab regin (60.7:60.7:60.7) (60.7:60.7:60.7))
        (IOPATH datac regin (47.8:47.8:47.8) (47.8:47.8:47.8))
        (IOPATH datad regin (30.9:30.9:30.9) (30.9:30.9:30.9))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|count\[3\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (89.8:89.8:89.8) (89.8:89.8:89.8))
        (PORT clk (145.6:145.6:145.6) (143.4:143.4:143.4))
        (PORT ena (154.3:154.3:154.3) (159.9:159.9:159.9))
        (IOPATH (posedge clk) regout (22.4:22.4:22.4) (22.4:22.4:22.4))
        (IOPATH (posedge aclr) regout (28.3:28.3:28.3) (28.3:28.3:28.3))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (3.7:3.7:3.7))
      (SETUP ena (posedge clk) (3.7:3.7:3.7))
      (HOLD datain (posedge clk) (1.5:1.5:1.5))
      (HOLD ena (posedge clk) (1.5:1.5:1.5))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|add\~226_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (126.5:126.5:126.5) (130.3:130.3:130.3))
        (IOPATH datab combout (44.2:44.2:44.2) (44.2:44.2:44.2))
        (IOPATH cin combout (62.1:62.1:62.1) (62.1:62.1:62.1))
        (IOPATH cin0 combout (60.4:60.4:60.4) (60.4:60.4:60.4))
        (IOPATH cin1 combout (60.8:60.8:60.8) (60.8:60.8:60.8))
        (IOPATH datab cout0 (42.3:42.3:42.3) (42.3:42.3:42.3))
        (IOPATH cin0 cout0 (7.8:7.8:7.8) (7.8:7.8:7.8))
        (IOPATH datab cout1 (43.2:43.2:43.2) (43.2:43.2:43.2))
        (IOPATH cin1 cout1 (8:8:8) (8:8:8))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|count\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (116.3:116.3:116.3) (121.1:121.1:121.1))
        (PORT datab (53.2:53.2:53.2) (53.5:53.5:53.5))
        (PORT datac (130.6:130.6:130.6) (135.4:135.4:135.4))
        (PORT datad (131.5:131.5:131.5) (130.9:130.9:130.9))
        (IOPATH dataa regin (73.8:73.8:73.8) (73.8:73.8:73.8))
        (IOPATH datab regin (60.7:60.7:60.7) (60.7:60.7:60.7))
        (IOPATH datac regin (47.8:47.8:47.8) (47.8:47.8:47.8))
        (IOPATH datad regin (30.9:30.9:30.9) (30.9:30.9:30.9))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|count\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (89.8:89.8:89.8) (89.8:89.8:89.8))
        (PORT clk (145.6:145.6:145.6) (143.4:143.4:143.4))
        (PORT ena (206.1:206.1:206.1) (215.5:215.5:215.5))
        (IOPATH (posedge clk) regout (22.4:22.4:22.4) (22.4:22.4:22.4))
        (IOPATH (posedge aclr) regout (28.3:28.3:28.3) (28.3:28.3:28.3))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (3.7:3.7:3.7))
      (SETUP ena (posedge clk) (3.7:3.7:3.7))
      (HOLD datain (posedge clk) (1.5:1.5:1.5))
      (HOLD ena (posedge clk) (1.5:1.5:1.5))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|add\~221_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (51.6:51.6:51.6) (52.9:52.9:52.9))
        (IOPATH dataa combout (59:59:59) (59:59:59))
        (IOPATH cin combout (62.1:62.1:62.1) (62.1:62.1:62.1))
        (IOPATH cin0 combout (60.4:60.4:60.4) (60.4:60.4:60.4))
        (IOPATH cin1 combout (60.8:60.8:60.8) (60.8:60.8:60.8))
        (IOPATH dataa cout (83.8:83.8:83.8) (83.8:83.8:83.8))
        (IOPATH cin cout (20.8:20.8:20.8) (20.8:20.8:20.8))
        (IOPATH cin0 cout (27.1:27.1:27.1) (27.1:27.1:27.1))
        (IOPATH cin1 cout (25.8:25.8:25.8) (25.8:25.8:25.8))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|count\[5\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (42.1:42.1:42.1) (43.5:43.5:43.5))
        (PORT datab (123:123:123) (126.8:126.8:126.8))
        (PORT datac (78.3:78.3:78.3) (79.2:79.2:79.2))
        (PORT datad (137.5:137.5:137.5) (138.9:138.9:138.9))
        (IOPATH dataa regin (73.8:73.8:73.8) (73.8:73.8:73.8))
        (IOPATH datab regin (60.7:60.7:60.7) (60.7:60.7:60.7))
        (IOPATH datac regin (47.8:47.8:47.8) (47.8:47.8:47.8))
        (IOPATH datad regin (30.9:30.9:30.9) (30.9:30.9:30.9))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|count\[5\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (89.8:89.8:89.8) (89.8:89.8:89.8))
        (PORT clk (145.6:145.6:145.6) (143.4:143.4:143.4))
        (PORT ena (154.3:154.3:154.3) (159.9:159.9:159.9))
        (IOPATH (posedge clk) regout (22.4:22.4:22.4) (22.4:22.4:22.4))
        (IOPATH (posedge aclr) regout (28.3:28.3:28.3) (28.3:28.3:28.3))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (3.7:3.7:3.7))
      (SETUP ena (posedge clk) (3.7:3.7:3.7))