_primary.vhd

典型事例

library verilog;
use verilog.vl_types.all;
entity WAVE is
    port(
        mclk            : in     vl_logic;
        altera_reserved_tms: in     vl_logic;
        altera_reserved_tck: in     vl_logic;
        altera_reserved_tdi: in     vl_logic;
        output          : out    vl_logic;
        address         : out    vl_logic_vector(5 downto 0);
        q               : out    vl_logic_vector(7 downto 0);
        altera_reserved_tdo: out    vl_logic
    );
end WAVE;