clock_1.tan.qmsg

简易数字钟

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk scan\[3\] cnt\[0\] 8.716 ns register " "Info: Minimum tco from clock \"clk\" to destination pin \"scan\[3\]\" through register \"cnt\[0\]\" is 8.716 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.812 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to source register is 2.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.812 ns cnt\[0\] 3 REG LCFF_X6_Y4_N17 19 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.812 ns; Loc. = LCFF_X6_Y4_N17; Fanout = 19; REG Node = 'cnt\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { clk~clkctrl cnt[0] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.45 % ) " "Info: Total cell delay = 1.756 ns ( 62.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.056 ns ( 37.55 % ) " "Info: Total interconnect delay = 1.056 ns ( 37.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.136ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 121 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns + Shortest register pin " "Info: + Shortest register to pin delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LCFF_X6_Y4_N17 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y4_N17; Fanout = 19; REG Node = 'cnt\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns Add4~37 2 COMB LCCOMB_X6_Y4_N16 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X6_Y4_N16; Fanout = 1; COMB Node = 'Add4~37'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { cnt[0] Add4~37 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.971 ns) + CELL(3.236 ns) 5.600 ns scan\[3\] 3 PIN PIN_70 0 " "Info: 3: + IC(1.971 ns) + CELL(3.236 ns) = 5.600 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'scan\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.207 ns" { Add4~37 scan[3] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.629 ns ( 64.80 % ) " "Info: Total cell delay = 3.629 ns ( 64.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.971 ns ( 35.20 % ) " "Info: Total interconnect delay = 1.971 ns ( 35.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { cnt[0] Add4~37 scan[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { cnt[0] Add4~37 scan[3] } { 0.000ns 0.000ns 1.971ns } { 0.000ns 0.393ns 3.236ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.136ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { cnt[0] Add4~37 scan[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { cnt[0] Add4~37 scan[3] } { 0.000ns 0.000ns 1.971ns } { 0.000ns 0.393ns 3.236ns } "" } }  } 0 0 "Minimum tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." {  } {  } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "117 " "Info: Allocated 117 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 18 11:04:18 2007 " "Info: Processing ended: Fri May 18 11:04:18 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}