📄 clock_1.tan.qmsg

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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[0\] register count\[7\] 144.84 MHz 6.904 ns Internal " "Info: Clock \"clk\" has Internal fmax of 144.84 MHz between source register \"cnt\[0\]\" and destination register \"count\[7\]\" (period= 6.904 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.620 ns + Longest register register " "Info: + Longest register to register delay is 6.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LCFF_X6_Y4_N17 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y4_N17; Fanout = 19; REG Node = 'cnt\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.983 ns) + CELL(0.596 ns) 4.579 ns Add0~115 2 COMB LCCOMB_X33_Y8_N16 2 " "Info: 2: + IC(3.983 ns) + CELL(0.596 ns) = 4.579 ns; Loc. = LCCOMB_X33_Y8_N16; Fanout = 2; COMB Node = 'Add0~115'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.579 ns" { cnt[0] Add0~115 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.665 ns Add0~117 3 COMB LCCOMB_X33_Y8_N18 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 4.665 ns; Loc. = LCCOMB_X33_Y8_N18; Fanout = 2; COMB Node = 'Add0~117'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~115 Add0~117 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.751 ns Add0~119 4 COMB LCCOMB_X33_Y8_N20 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 4.751 ns; Loc. = LCCOMB_X33_Y8_N20; Fanout = 2; COMB Node = 'Add0~119'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~117 Add0~119 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.837 ns Add0~121 5 COMB LCCOMB_X33_Y8_N22 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 4.837 ns; Loc. = LCCOMB_X33_Y8_N22; Fanout = 2; COMB Node = 'Add0~121'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~119 Add0~121 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.923 ns Add0~123 6 COMB LCCOMB_X33_Y8_N24 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 4.923 ns; Loc. = LCCOMB_X33_Y8_N24; Fanout = 2; COMB Node = 'Add0~123'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~121 Add0~123 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.009 ns Add0~125 7 COMB LCCOMB_X33_Y8_N26 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 5.009 ns; Loc. = LCCOMB_X33_Y8_N26; Fanout = 2; COMB Node = 'Add0~125'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~123 Add0~125 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 5.515 ns Add0~126 8 COMB LCCOMB_X33_Y8_N28 1 " "Info: 8: + IC(0.000 ns) + CELL(0.506 ns) = 5.515 ns; Loc. = LCCOMB_X33_Y8_N28; Fanout = 1; COMB Node = 'Add0~126'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~125 Add0~126 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.624 ns) 6.512 ns count~268 9 COMB LCCOMB_X33_Y8_N0 1 " "Info: 9: + IC(0.373 ns) + CELL(0.624 ns) = 6.512 ns; Loc. = LCCOMB_X33_Y8_N0; Fanout = 1; COMB Node = 'count~268'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.997 ns" { Add0~126 count~268 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.620 ns count\[7\] 10 REG LCFF_X33_Y8_N1 3 " "Info: 10: + IC(0.000 ns) + CELL(0.108 ns) = 6.620 ns; Loc. = LCFF_X33_Y8_N1; Fanout = 3; REG Node = 'count\[7\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { count~268 count[7] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.264 ns ( 34.20 % ) " "Info: Total cell delay = 2.264 ns ( 34.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.356 ns ( 65.80 % ) " "Info: Total interconnect delay = 4.356 ns ( 65.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.620 ns" { cnt[0] Add0~115 Add0~117 Add0~119 Add0~121 Add0~123 Add0~125 Add0~126 count~268 count[7] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.620 ns" { cnt[0] Add0~115 Add0~117 Add0~119 Add0~121 Add0~123 Add0~125 Add0~126 count~268 count[7] } { 0.000ns 3.983ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.373ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.792 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.666 ns) 2.792 ns count\[7\] 3 REG LCFF_X33_Y8_N1 3 " "Info: 3: + IC(0.900 ns) + CELL(0.666 ns) = 2.792 ns; Loc. = LCFF_X33_Y8_N1; Fanout = 3; REG Node = 'count\[7\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { clk~clkctrl count[7] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.89 % ) " "Info: Total cell delay = 1.756 ns ( 62.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.036 ns ( 37.11 % ) " "Info: Total interconnect delay = 1.036 ns ( 37.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.792 ns" { clk clk~clkctrl count[7] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.792 ns" { clk clk~combout clk~clkctrl count[7] } { 0.000ns 0.000ns 0.136ns 0.900ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.812 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.812 ns cnt\[0\] 3 REG LCFF_X6_Y4_N17 19 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.812 ns; Loc. = LCFF_X6_Y4_N17; Fanout = 19; REG Node = 'cnt\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { clk~clkctrl cnt[0] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.45 % ) " "Info: Total cell delay = 1.756 ns ( 62.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.056 ns ( 37.55 % ) " "Info: Total interconnect delay = 1.056 ns ( 37.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.136ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.792 ns" { clk clk~clkctrl count[7] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.792 ns" { clk clk~combout clk~clkctrl count[7] } { 0.000ns 0.000ns 0.136ns 0.900ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.136ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 121 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.620 ns" { cnt[0] Add0~115 Add0~117 Add0~119 Add0~121 Add0~123 Add0~125 Add0~126 count~268 count[7] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.620 ns" { cnt[0] Add0~115 Add0~117 Add0~119 Add0~121 Add0~123 Add0~125 Add0~126 count~268 count[7] } { 0.000ns 3.983ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.373ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.624ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.792 ns" { clk clk~clkctrl count[7] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.792 ns" { clk clk~combout clk~clkctrl count[7] } { 0.000ns 0.000ns 0.136ns 0.900ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.136ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "hour\[1\] en clk 4.484 ns register " "Info: tsu for register \"hour\[1\]\" (data pin = \"en\", clock pin = \"clk\") is 4.484 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.373 ns + Longest pin register " "Info: + Longest pin to register delay is 10.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns en 1 PIN PIN_64 8 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_64; Fanout = 8; PIN Node = 'en'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.306 ns) + CELL(0.370 ns) 7.620 ns min\[5\]~374 2 COMB LCCOMB_X30_Y9_N24 7 " "Info: 2: + IC(6.306 ns) + CELL(0.370 ns) = 7.620 ns; Loc. = LCCOMB_X30_Y9_N24; Fanout = 7; COMB Node = 'min\[5\]~374'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.676 ns" { en min[5]~374 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.206 ns) 8.497 ns hour\[4\]~265 3 COMB LCCOMB_X31_Y9_N30 5 " "Info: 3: + IC(0.671 ns) + CELL(0.206 ns) = 8.497 ns; Loc. = LCCOMB_X31_Y9_N30; Fanout = 5; COMB Node = 'hour\[4\]~265'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.877 ns" { min[5]~374 hour[4]~265 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.855 ns) 10.373 ns hour\[1\] 4 REG LCFF_X31_Y8_N15 7 " "Info: 4: + IC(1.021 ns) + CELL(0.855 ns) = 10.373 ns; Loc. = LCFF_X31_Y8_N15; Fanout = 7; REG Node = 'hour\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.876 ns" { hour[4]~265 hour[1] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.375 ns ( 22.90 % ) " "Info: Total cell delay = 2.375 ns ( 22.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.998 ns ( 77.10 % ) " "Info: Total interconnect delay = 7.998 ns ( 77.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.373 ns" { en min[5]~374 hour[4]~265 hour[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.373 ns" { en en~combout min[5]~374 hour[4]~265 hour[1] } { 0.000ns 0.000ns 6.306ns 0.671ns 1.021ns } { 0.000ns 0.944ns 0.370ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.849 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 5.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.970 ns) 3.096 ns clk1hz 3 REG LCFF_X33_Y8_N9 2 " "Info: 3: + IC(0.900 ns) + CELL(0.970 ns) = 3.096 ns; Loc. = LCFF_X33_Y8_N9; Fanout = 2; REG Node = 'clk1hz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.870 ns" { clk~clkctrl clk1hz } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.000 ns) 4.283 ns clk1hz~clkctrl 4 COMB CLKCTRL_G6 17 " "Info: 4: + IC(1.187 ns) + CELL(0.000 ns) = 4.283 ns; Loc. = CLKCTRL_G6; Fanout = 17; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.666 ns) 5.849 ns hour\[1\] 5 REG LCFF_X31_Y8_N15 7 " "Info: 5: + IC(0.900 ns) + CELL(0.666 ns) = 5.849 ns; Loc. = LCFF_X31_Y8_N15; Fanout = 7; REG Node = 'hour\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { clk1hz~clkctrl hour[1] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 46.61 % ) " "Info: Total cell delay = 2.726 ns ( 46.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.123 ns ( 53.39 % ) " "Info: Total interconnect delay = 3.123 ns ( 53.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.849 ns" { clk clk~clkctrl clk1hz clk1hz~clkctrl hour[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.849 ns" { clk clk~combout clk~clkctrl clk1hz clk1hz~clkctrl hour[1] } { 0.000ns 0.000ns 0.136ns 0.900ns 1.187ns 0.900ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.373 ns" { en min[5]~374 hour[4]~265 hour[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.373 ns" { en en~combout min[5]~374 hour[4]~265 hour[1] } { 0.000ns 0.000ns 6.306ns 0.671ns 1.021ns } { 0.000ns 0.944ns 0.370ns 0.206ns 0.855ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.849 ns" { clk clk~clkctrl clk1hz clk1hz~clkctrl hour[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.849 ns" { clk clk~combout clk~clkctrl clk1hz clk1hz~clkctrl hour[1] } { 0.000ns 0.000ns 0.136ns 0.900ns 1.187ns 0.900ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register cnt\[0\] pin scan\[4\] 324 ps " "Info: Slack time is 324 ps for clock \"clk\" between source register \"cnt\[0\]\" and destination pin \"scan\[4\]\"" { { "Info" "ITDB_FULL_TCO_REQUIREMENT" "10.000 ns + register " "Info: + tco requirement for source register and destination pin is 10.000 ns" {  } {  } 0 0 "%2!c! tco requirement for source %3!s! and destination pin is %1!s!" 0 0} { "Info" "ITDB_SLACK_TCO_RESULT" "9.676 ns - " "Info: - tco from clock to output pin is 9.676 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.812 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.812 ns cnt\[0\] 3 REG LCFF_X6_Y4_N17 19 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.812 ns; Loc. = LCFF_X6_Y4_N17; Fanout = 19; REG Node = 'cnt\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { clk~clkctrl cnt[0] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.45 % ) " "Info: Total cell delay = 1.756 ns ( 62.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.056 ns ( 37.55 % ) " "Info: Total interconnect delay = 1.056 ns ( 37.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.136ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 121 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.560 ns + Longest register pin " "Info: + Longest register to pin delay is 6.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LCFF_X6_Y4_N17 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y4_N17; Fanout = 19; REG Node = 'cnt\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.202 ns) 0.969 ns Mux22~18 2 COMB LCCOMB_X6_Y4_N14 1 " "Info: 2: + IC(0.767 ns) + CELL(0.202 ns) = 0.969 ns; Loc. = LCCOMB_X6_Y4_N14; Fanout = 1; COMB Node = 'Mux22~18'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.969 ns" { cnt[0] Mux22~18 } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.345 ns) + CELL(3.246 ns) 6.560 ns scan\[4\] 3 PIN PIN_71 0 " "Info: 3: + IC(2.345 ns) + CELL(3.246 ns) = 6.560 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'scan\[4\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.591 ns" { Mux22~18 scan[4] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.448 ns ( 52.56 % ) " "Info: Total cell delay = 3.448 ns ( 52.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.112 ns ( 47.44 % ) " "Info: Total interconnect delay = 3.112 ns ( 47.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.560 ns" { cnt[0] Mux22~18 scan[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.560 ns" { cnt[0] Mux22~18 scan[4] } { 0.000ns 0.767ns 2.345ns } { 0.000ns 0.202ns 3.246ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.136ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.560 ns" { cnt[0] Mux22~18 scan[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.560 ns" { cnt[0] Mux22~18 scan[4] } { 0.000ns 0.767ns 2.345ns } { 0.000ns 0.202ns 3.246ns } "" } }  } 0 0 "%2!c! tco from clock to output pin is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.136ns 0.920ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.560 ns" { cnt[0] Mux22~18 scan[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.560 ns" { cnt[0] Mux22~18 scan[4] } { 0.000ns 0.767ns 2.345ns } { 0.000ns 0.202ns 3.246ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TH_RESULT" "sec\[0\] en clk -1.916 ns register " "Info: th for register \"sec\[0\]\" (data pin = \"en\", clock pin = \"clk\") is -1.916 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.830 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.136 ns) + CELL(0.000 ns) 1.226 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.136 ns) + CELL(0.000 ns) = 1.226 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.970 ns) 3.096 ns clk1hz 3 REG LCFF_X33_Y8_N9 2 " "Info: 3: + IC(0.900 ns) + CELL(0.970 ns) = 3.096 ns; Loc. = LCFF_X33_Y8_N9; Fanout = 2; REG Node = 'clk1hz'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.870 ns" { clk~clkctrl clk1hz } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.000 ns) 4.283 ns clk1hz~clkctrl 4 COMB CLKCTRL_G6 17 " "Info: 4: + IC(1.187 ns) + CELL(0.000 ns) = 4.283 ns; Loc. = CLKCTRL_G6; Fanout = 17; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.881 ns) + CELL(0.666 ns) 5.830 ns sec\[0\] 5 REG LCFF_X30_Y9_N7 8 " "Info: 5: + IC(0.881 ns) + CELL(0.666 ns) = 5.830 ns; Loc. = LCFF_X30_Y9_N7; Fanout = 8; REG Node = 'sec\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.547 ns" { clk1hz~clkctrl sec[0] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 46.76 % ) " "Info: Total cell delay = 2.726 ns ( 46.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.104 ns ( 53.24 % ) " "Info: Total interconnect delay = 3.104 ns ( 53.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.830 ns" { clk clk~clkctrl clk1hz clk1hz~clkctrl sec[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.830 ns" { clk clk~combout clk~clkctrl clk1hz clk1hz~clkctrl sec[0] } { 0.000ns 0.000ns 0.136ns 0.900ns 1.187ns 0.881ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.052 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.052 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns en 1 PIN PIN_64 8 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_64; Fanout = 8; PIN Node = 'en'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.253 ns) + CELL(0.855 ns) 8.052 ns sec\[0\] 2 REG LCFF_X30_Y9_N7 8 " "Info: 2: + IC(6.253 ns) + CELL(0.855 ns) = 8.052 ns; Loc. = LCFF_X30_Y9_N7; Fanout = 8; REG Node = 'sec\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.108 ns" { en sec[0] } "NODE_NAME" } } { "clock_1.vhd" "" { Text "D:/my_eda2/clock_1/clock_1.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.799 ns ( 22.34 % ) " "Info: Total cell delay = 1.799 ns ( 22.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.253 ns ( 77.66 % ) " "Info: Total interconnect delay = 6.253 ns ( 77.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.052 ns" { en sec[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.052 ns" { en en~combout sec[0] } { 0.000ns 0.000ns 6.253ns } { 0.000ns 0.944ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.830 ns" { clk clk~clkctrl clk1hz clk1hz~clkctrl sec[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.830 ns" { clk clk~combout clk~clkctrl clk1hz clk1hz~clkctrl sec[0] } { 0.000ns 0.000ns 0.136ns 0.900ns 1.187ns 0.881ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.052 ns" { en sec[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.052 ns" { en en~combout sec[0] } { 0.000ns 0.000ns 6.253ns } { 0.000ns 0.944ns 0.855ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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