clock_1.sim.rpt

简易数字钟

; |clock_1|seg[3]         ; |clock_1|seg[3]         ; padio            ;
; |clock_1|seg[4]         ; |clock_1|seg[4]         ; padio            ;
; |clock_1|seg[5]         ; |clock_1|seg[5]         ; padio            ;
; |clock_1|seg[6]         ; |clock_1|seg[6]         ; padio            ;
; |clock_1|scan[0]        ; |clock_1|scan[0]        ; padio            ;
; |clock_1|scan[1]        ; |clock_1|scan[1]        ; padio            ;
; |clock_1|scan[2]        ; |clock_1|scan[2]        ; padio            ;
; |clock_1|scan[3]        ; |clock_1|scan[3]        ; padio            ;
; |clock_1|scan[4]        ; |clock_1|scan[4]        ; padio            ;
; |clock_1|scan[5]        ; |clock_1|scan[5]        ; padio            ;
; |clock_1|clk1hz~clkctrl ; |clock_1|clk1hz~clkctrl ; outclk           ;
; |clock_1|clk~clkctrl    ; |clock_1|clk~clkctrl    ; outclk           ;
+-------------------------+-------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------+
; Missing 1-Value Coverage                                           ;
+------------------------+------------------------+------------------+
; Node Name              ; Output Port Name       ; Output Port Type ;
+------------------------+------------------------+------------------+
; |clock_1|min[0]        ; |clock_1|min[0]        ; regout           ;
; |clock_1|sec[5]        ; |clock_1|sec[5]        ; regout           ;
; |clock_1|min[1]        ; |clock_1|min[1]        ; regout           ;
; |clock_1|min[2]        ; |clock_1|min[2]        ; regout           ;
; |clock_1|min[3]        ; |clock_1|min[3]        ; regout           ;
; |clock_1|min[4]        ; |clock_1|min[4]        ; regout           ;
; |clock_1|Mux11~50      ; |clock_1|Mux11~50      ; combout          ;
; |clock_1|min[5]        ; |clock_1|min[5]        ; regout           ;
; |clock_1|Mux11~51      ; |clock_1|Mux11~51      ; combout          ;
; |clock_1|Mux11~52      ; |clock_1|Mux11~52      ; combout          ;
; |clock_1|hour[1]       ; |clock_1|hour[1]       ; regout           ;
; |clock_1|hour[2]       ; |clock_1|hour[2]       ; regout           ;
; |clock_1|hour[3]       ; |clock_1|hour[3]       ; regout           ;
; |clock_1|hour[4]       ; |clock_1|hour[4]       ; regout           ;
; |clock_1|Mux16~19      ; |clock_1|Mux16~19      ; combout          ;
; |clock_1|hour[0]       ; |clock_1|hour[0]       ; regout           ;
; |clock_1|Mux20~148     ; |clock_1|Mux20~148     ; combout          ;
; |clock_1|Mux8~47       ; |clock_1|Mux8~47       ; combout          ;
; |clock_1|Mux8~48       ; |clock_1|Mux8~48       ; combout          ;
; |clock_1|Mux8~49       ; |clock_1|Mux8~49       ; combout          ;
; |clock_1|Mux10~16      ; |clock_1|Mux10~16      ; combout          ;
; |clock_1|Mux14~19      ; |clock_1|Mux14~19      ; combout          ;
; |clock_1|Mux19~145     ; |clock_1|Mux19~145     ; combout          ;
; |clock_1|Mux7~47       ; |clock_1|Mux7~47       ; combout          ;
; |clock_1|Mux7~48       ; |clock_1|Mux7~48       ; combout          ;
; |clock_1|Mux7~49       ; |clock_1|Mux7~49       ; combout          ;
; |clock_1|Mux3~20       ; |clock_1|Mux3~20       ; combout          ;
; |clock_1|Mux9~20       ; |clock_1|Mux9~20       ; combout          ;
; |clock_1|Mux13~17      ; |clock_1|Mux13~17      ; combout          ;
; |clock_1|Mux18~49      ; |clock_1|Mux18~49      ; combout          ;
; |clock_1|Mux6~31       ; |clock_1|Mux6~31       ; combout          ;
; |clock_1|Mux6~32       ; |clock_1|Mux6~32       ; combout          ;
; |clock_1|Mux17~431     ; |clock_1|Mux17~431     ; combout          ;
; |clock_1|Mux12~13      ; |clock_1|Mux12~13      ; combout          ;
; |clock_1|Add2~72       ; |clock_1|Add2~72       ; combout          ;
; |clock_1|Add2~72       ; |clock_1|Add2~73       ; cout             ;
; |clock_1|comb~1        ; |clock_1|comb~1        ; combout          ;
; |clock_1|Equal1~48     ; |clock_1|Equal1~48     ; combout          ;
; |clock_1|min[5]~374    ; |clock_1|min[5]~374    ; combout          ;
; |clock_1|Add3~80       ; |clock_1|Add3~81       ; cout             ;
; |clock_1|Add3~82       ; |clock_1|Add3~82       ; combout          ;
; |clock_1|sec~355       ; |clock_1|sec~355       ; combout          ;
; |clock_1|Add2~74       ; |clock_1|Add2~74       ; combout          ;
; |clock_1|Add2~74       ; |clock_1|Add2~75       ; cout             ;
; |clock_1|Add2~76       ; |clock_1|Add2~76       ; combout          ;
; |clock_1|Add2~76       ; |clock_1|Add2~77       ; cout             ;
; |clock_1|Equal2~48     ; |clock_1|Equal2~48     ; combout          ;
; |clock_1|min~375       ; |clock_1|min~375       ; combout          ;
; |clock_1|Add2~78       ; |clock_1|Add2~78       ; combout          ;
; |clock_1|Add2~78       ; |clock_1|Add2~79       ; cout             ;
; |clock_1|min~376       ; |clock_1|min~376       ; combout          ;
; |clock_1|Add2~80       ; |clock_1|Add2~80       ; combout          ;
; |clock_1|Add2~80       ; |clock_1|Add2~81       ; cout             ;
; |clock_1|min~377       ; |clock_1|min~377       ; combout          ;
; |clock_1|Add2~82       ; |clock_1|Add2~82       ; combout          ;
; |clock_1|min~378       ; |clock_1|min~378       ; combout          ;
; |clock_1|Add1~60       ; |clock_1|Add1~60       ; combout          ;
; |clock_1|Add1~60       ; |clock_1|Add1~61       ; cout             ;
; |clock_1|Add1~62       ; |clock_1|Add1~62       ; combout          ;
; |clock_1|Add1~62       ; |clock_1|Add1~63       ; cout             ;
; |clock_1|hour[4]~265   ; |clock_1|hour[4]~265   ; combout          ;
; |clock_1|Add1~64       ; |clock_1|Add1~64       ; combout          ;
; |clock_1|Add1~64       ; |clock_1|Add1~65       ; cout             ;
; |clock_1|Add1~66       ; |clock_1|Add1~66       ; combout          ;
; |clock_1|Add1~66       ; |clock_1|Add1~67       ; cout             ;
; |clock_1|Equal3~36     ; |clock_1|Equal3~36     ; combout          ;
; |clock_1|hour~266      ; |clock_1|hour~266      ; combout          ;
; |clock_1|Add1~68       ; |clock_1|Add1~68       ; combout          ;
; |clock_1|hour~267      ; |clock_1|hour~267      ; combout          ;
; |clock_1|clr           ; |clock_1|clr           ; combout          ;
; |clock_1|en            ; |clock_1|en            ; combout          ;
; |clock_1|comb~1clkctrl ; |clock_1|comb~1clkctrl ; outclk           ;
+------------------------+------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------+
; Missing 0-Value Coverage                                           ;
+------------------------+------------------------+------------------+
; Node Name              ; Output Port Name       ; Output Port Type ;
+------------------------+------------------------+------------------+
; |clock_1|min[0]        ; |clock_1|min[0]        ; regout           ;
; |clock_1|sec[4]        ; |clock_1|sec[4]        ; regout           ;
; |clock_1|sec[5]        ; |clock_1|sec[5]        ; regout           ;
; |clock_1|min[1]        ; |clock_1|min[1]        ; regout           ;
; |clock_1|min[2]        ; |clock_1|min[2]        ; regout           ;
; |clock_1|min[3]        ; |clock_1|min[3]        ; regout           ;
; |clock_1|min[4]        ; |clock_1|min[4]        ; regout           ;
; |clock_1|Mux11~50      ; |clock_1|Mux11~50      ; combout          ;
; |clock_1|min[5]        ; |clock_1|min[5]        ; regout           ;
; |clock_1|Mux11~51      ; |clock_1|Mux11~51      ; combout          ;
; |clock_1|Mux11~52      ; |clock_1|Mux11~52      ; combout          ;
; |clock_1|hour[1]       ; |clock_1|hour[1]       ; regout           ;
; |clock_1|hour[2]       ; |clock_1|hour[2]       ; regout           ;
; |clock_1|hour[3]       ; |clock_1|hour[3]       ; regout           ;
; |clock_1|hour[4]       ; |clock_1|hour[4]       ; regout           ;
; |clock_1|Mux16~19      ; |clock_1|Mux16~19      ; combout          ;
; |clock_1|hour[0]       ; |clock_1|hour[0]       ; regout           ;
; |clock_1|Mux20~148     ; |clock_1|Mux20~148     ; combout          ;
; |clock_1|Mux8~47       ; |clock_1|Mux8~47       ; combout          ;
; |clock_1|Mux8~48       ; |clock_1|Mux8~48       ; combout          ;
; |clock_1|Mux8~49       ; |clock_1|Mux8~49       ; combout          ;
; |clock_1|Mux10~16      ; |clock_1|Mux10~16      ; combout          ;
; |clock_1|Mux14~19      ; |clock_1|Mux14~19      ; combout          ;
; |clock_1|Mux19~145     ; |clock_1|Mux19~145     ; combout          ;
; |clock_1|Mux7~47       ; |clock_1|Mux7~47       ; combout          ;
; |clock_1|Mux7~48       ; |clock_1|Mux7~48       ; combout          ;
; |clock_1|Mux7~49       ; |clock_1|Mux7~49       ; combout          ;
; |clock_1|Mux3~20       ; |clock_1|Mux3~20       ; combout          ;
; |clock_1|Mux9~20       ; |clock_1|Mux9~20       ; combout          ;
; |clock_1|Mux13~17      ; |clock_1|Mux13~17      ; combout          ;
; |clock_1|Mux18~49      ; |clock_1|Mux18~49      ; combout          ;
; |clock_1|Mux6~31       ; |clock_1|Mux6~31       ; combout          ;
; |clock_1|Mux6~32       ; |clock_1|Mux6~32       ; combout          ;
; |clock_1|Mux17~431     ; |clock_1|Mux17~431     ; combout          ;
; |clock_1|Mux12~13      ; |clock_1|Mux12~13      ; combout          ;
; |clock_1|Add2~72       ; |clock_1|Add2~72       ; combout          ;
; |clock_1|Add2~72       ; |clock_1|Add2~73       ; cout             ;
; |clock_1|comb~1        ; |clock_1|comb~1        ; combout          ;
; |clock_1|Equal1~48     ; |clock_1|Equal1~48     ; combout          ;
; |clock_1|min[5]~374    ; |clock_1|min[5]~374    ; combout          ;
; |clock_1|Add3~80       ; |clock_1|Add3~81       ; cout             ;
; |clock_1|Add3~82       ; |clock_1|Add3~82       ; combout          ;
; |clock_1|sec~355       ; |clock_1|sec~355       ; combout          ;
; |clock_1|Add2~74       ; |clock_1|Add2~74       ; combout          ;
; |clock_1|Add2~74       ; |clock_1|Add2~75       ; cout             ;
; |clock_1|Add2~76       ; |clock_1|Add2~76       ; combout          ;
; |clock_1|Add2~76       ; |clock_1|Add2~77       ; cout             ;
; |clock_1|Equal2~48     ; |clock_1|Equal2~48     ; combout          ;
; |clock_1|min~375       ; |clock_1|min~375       ; combout          ;
; |clock_1|Add2~78       ; |clock_1|Add2~78       ; combout          ;
; |clock_1|Add2~78       ; |clock_1|Add2~79       ; cout             ;
; |clock_1|min~376       ; |clock_1|min~376       ; combout          ;
; |clock_1|Add2~80       ; |clock_1|Add2~80       ; combout          ;
; |clock_1|Add2~80       ; |clock_1|Add2~81       ; cout             ;
; |clock_1|min~377       ; |clock_1|min~377       ; combout          ;
; |clock_1|Add2~82       ; |clock_1|Add2~82       ; combout          ;
; |clock_1|min~378       ; |clock_1|min~378       ; combout          ;
; |clock_1|Add1~60       ; |clock_1|Add1~60       ; combout          ;
; |clock_1|Add1~60       ; |clock_1|Add1~61       ; cout             ;
; |clock_1|Add1~62       ; |clock_1|Add1~62       ; combout          ;
; |clock_1|Add1~62       ; |clock_1|Add1~63       ; cout             ;
; |clock_1|hour[4]~265   ; |clock_1|hour[4]~265   ; combout          ;
; |clock_1|Add1~64       ; |clock_1|Add1~64       ; combout          ;
; |clock_1|Add1~64       ; |clock_1|Add1~65       ; cout             ;
; |clock_1|Add1~66       ; |clock_1|Add1~66       ; combout          ;
; |clock_1|Add1~66       ; |clock_1|Add1~67       ; cout             ;
; |clock_1|Equal3~36     ; |clock_1|Equal3~36     ; combout          ;
; |clock_1|hour~266      ; |clock_1|hour~266      ; combout          ;
; |clock_1|Add1~68       ; |clock_1|Add1~68       ; combout          ;
; |clock_1|hour~267      ; |clock_1|hour~267      ; combout          ;
; |clock_1|clr           ; |clock_1|clr           ; combout          ;
; |clock_1|en            ; |clock_1|en            ; combout          ;
; |clock_1|comb~1clkctrl ; |clock_1|comb~1clkctrl ; outclk           ;
+------------------------+------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue May 15 21:03:31 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off clock_1 -c clock_1
Info: Using vector source file "D:/my_eda2/clock_1/clock_1.vwf"
Info: Overwriting simulation input file with simulation results
    Info: A backup of clock_1.vwf called clock_1.sim_ori.vwf has been created in the db folder
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      59.67 %
Info: Number of transitions in simulation is 1092214
Info: Vector file clock_1.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 92 megabytes of memory during processing
    Info: Processing ended: Tue May 15 21:03:57 2007
    Info: Elapsed time: 00:00:26