hdlc_top.vhd

在通讯领域中使用相当广泛的HDLC

    port map(
	RST	     => RST,
    	CPU_Data_In  => CPU_Data, 
	CPU_Data_Out => CPU_Data_L4,
    	CPU_Add	     => CPU_Add(2 downto 0),    
    	CPU_WRn	     => CPU_WRn,                       
    	CPU_DSn	     => CH_DSn,	
    	CPU_WR_DSn   => CH_WR_DSn,		    
   	CPU_CS	     => CH_CS(4),
    	CPU_INTn     => CPU_INTn4,
	CPU_clk	     => CH_clk,				
	RxClk        => RxClk, 
    	RxData       => RxData4, 
	TxClk        => TxClk, 
    	TxData       => TxData4a);    	
CH5_Port : SC_HDLC 
    port map(
	RST	     => RST,
    	CPU_Data_In  => CPU_Data, 
	CPU_Data_Out => CPU_Data_L5,
    	CPU_Add	     => CPU_Add(2 downto 0),    
    	CPU_WRn	     => CPU_WRn,                       
    	CPU_DSn	     => CH_DSn,	
    	CPU_WR_DSn   => CH_WR_DSn,		    
   	CPU_CS	     => CH_CS(5),
    	CPU_INTn     => CPU_INTn5,
	CPU_clk	     => CH_clk,				
	RxClk        => RxClk, 
    	RxData       => RxData5, 
	TxClk        => TxClk, 
    	TxData       => TxData5a);    	
CH6_Port : SC_HDLC 
    port map(
	RST	     => RST,
    	CPU_Data_In  => CPU_Data, 
	CPU_Data_Out => CPU_Data_L6,
    	CPU_Add	     => CPU_Add(2 downto 0),    
    	CPU_WRn	     => CPU_WRn,                       
    	CPU_DSn	     => CH_DSn,	
    	CPU_WR_DSn   => CH_WR_DSn,		    
   	CPU_CS	     => CH_CS(6),
    	CPU_INTn     => CPU_INTn6,
	CPU_clk	     => CH_clk,				
	RxClk        => RxClk, 
    	RxData       => RxData6, 
	TxClk        => TxClk, 
    	TxData       => TxData6a);
CH7_Port : SC_HDLC 
    port map(
	RST	     => RST,
    	CPU_Data_In  => CPU_Data, 
	CPU_Data_Out => CPU_Data_L7,
    	CPU_Add	     => CPU_Add(2 downto 0),    
    	CPU_WRn	     => CPU_WRn,                       
    	CPU_DSn	     => CH_DSn,	
    	CPU_WR_DSn   => CH_WR_DSn,		    
   	CPU_CS	     => CH_CS(7),
    	CPU_INTn     => CPU_INTn7,
	CPU_clk	     => CH_clk,				
	RxClk        => RxClk, 
    	RxData       => RxData7, 
	TxClk        => TxClk, 
    	TxData       => TxData7a);    	
CH8_Port : SC_HDLC 
    port map(
	RST	     => RST,
    	CPU_Data_In  => CPU_Data, 
	CPU_Data_Out => CPU_Data_L8,
    	CPU_Add	     => CPU_Add(2 downto 0),    
    	CPU_WRn	     => CPU_WRn,                       
    	CPU_DSn	     => CH_DSn,	
    	CPU_WR_DSn   => CH_WR_DSn,		    
   	CPU_CS	     => CH_CS(8),
    	CPU_INTn     => CPU_INTn8,
	CPU_clk	     => CH_clk,				
	RxClk        => RxClk, 
    	RxData       => RxData8, 
	TxClk        => TxClk, 
    	TxData       => TxData8a);    	
CH9_Port : SC_HDLC 
    port map(
	RST	     => RST,
    	CPU_Data_In  => CPU_Data, 
	CPU_Data_Out => CPU_Data_L9,
    	CPU_Add	     => CPU_Add(2 downto 0),    
    	CPU_WRn	     => CPU_WRn,                       
    	CPU_DSn	     => CH_DSn,	
    	CPU_WR_DSn   => CH_WR_DSn,		    
   	CPU_CS	     => CH_CS(9),
    	CPU_INTn     => CPU_INTn9,
	CPU_clk	     => CH_clk,				
	RxClk        => RxClk, 
    	RxData       => RxData9, 
	TxClk        => TxClk, 
    	TxData       => TxData9a);    	
CH10_Port : SC_HDLC 
    port map(
	RST	     => RST,
    	CPU_Data_In  => CPU_Data, 
	CPU_Data_Out => CPU_Data_L10,
    	CPU_Add	     => CPU_Add(2 downto 0),    
    	CPU_WRn	     => CPU_WRn,                       
    	CPU_DSn	     => CH_DSn,	
    	CPU_WR_DSn   => CH_WR_DSn,		    
   	CPU_CS	     => CH_CS(10),
    	CPU_INTn     => CPU_INTn10,
	CPU_clk	     => CH_clk,				
	RxClk        => RxClk, 
    	RxData       => RxData10, 
	TxClk        => TxClk, 
    	TxData       => TxData10a);
CH11_Port : SC_HDLC 
    port map(
	RST	     => RST,
    	CPU_Data_In  => CPU_Data, 
	CPU_Data_Out => CPU_Data_L11,
    	CPU_Add	     => CPU_Add(2 downto 0),    
    	CPU_WRn	     => CPU_WRn,                       
    	CPU_DSn	     => CH_DSn,	
    	CPU_WR_DSn   => CH_WR_DSn,		    
   	CPU_CS	     => CH_CS(11),
    	CPU_INTn     => CPU_INTn11,
	CPU_clk	     => CH_clk,				
	RxClk        => RxClk, 
    	RxData       => RxData11, 
	TxClk        => TxClk, 
    	TxData       => TxData11a);    	
CH12_Port : SC_HDLC 
    port map(
	RST	     => RST,
    	CPU_Data_In  => CPU_Data, 
	CPU_Data_Out => CPU_Data_L12,
    	CPU_Add	     => CPU_Add(2 downto 0),    
    	CPU_WRn	     => CPU_WRn,                       
    	CPU_DSn	     => CH_DSn,	
    	CPU_WR_DSn   => CH_WR_DSn,		    
   	CPU_CS	     => CH_CS(12),
    	CPU_INTn     => CPU_INTn12,
	CPU_clk	     => CH_clk,				
	RxClk        => RxClk, 
    	RxData       => RxData12, 
	TxClk        => TxClk, 
    	TxData       => TxData12a);     	
--=====================================================================================



--======================= channel 0 hdlc txdata modulation ============================
Process(RST, CLK, Int0_reg)
begin
	if rst = '0' then
		Int0_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int0_reg(14 downto 0) = "011111011111100") then
			Int0_reg(16 downto 0) <= int0_reg(15) & "011111001111110" & txdata0a;
			
		else
			Int0_reg(16 downto 0) <= Int0_reg(15 downto 0) & txdata0a;
		end if;
	end if;
end process;

txdata0 <= int0_reg(16);
--=====================================================================================
--======================= channel 1 hdlc txdata modulation ============================
Process(RST, CLK, Int1_reg)
begin
	if rst = '0' then
		Int1_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int1_reg(14 downto 0) = "011111011111100") then
			Int1_reg(16 downto 0) <= int1_reg(15) & "011111001111110" & txdata1a;
			
		else
			Int1_reg(16 downto 0) <= Int1_reg(15 downto 0) & txdata1a;
		end if;
	end if;
end process;

txdata1 <= int1_reg(16);
--=====================================================================================
--======================= channel 2 hdlc txdata modulation ============================
Process(RST, CLK, Int2_reg)
begin
	if rst = '0' then
		Int2_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int2_reg(14 downto 0) = "011111011111100") then
			Int2_reg(16 downto 0) <= int2_reg(15) & "011111001111110" & txdata2a;
			
		else
			Int2_reg(16 downto 0) <= Int2_reg(15 downto 0) & txdata2a;
		end if;
	end if;
end process;

txdata2 <= int2_reg(16);
--=====================================================================================
--======================= channel 3 hdlc txdata modulation ============================
Process(RST, CLK, Int3_reg)
begin
	if rst = '0' then
		Int3_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int3_reg(14 downto 0) = "011111011111100") then
			Int3_reg(16 downto 0) <= int3_reg(15) & "011111001111110" & txdata3a;
			
		else
			Int3_reg(16 downto 0) <= Int3_reg(15 downto 0) & txdata3a;
		end if;
	end if;
end process;

txdata3 <= int3_reg(16);
--=====================================================================================
--======================= channel 4 hdlc txdata modulation ============================
Process(RST, CLK, Int4_reg)
begin
	if rst = '0' then
		Int4_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int4_reg(14 downto 0) = "011111011111100") then
			Int4_reg(16 downto 0) <= int4_reg(15) & "011111001111110" & txdata4a;
			
		else
			Int4_reg(16 downto 0) <= Int4_reg(15 downto 0) & txdata4a;
		end if;
	end if;
end process;

txdata4 <= int4_reg(16);
--=====================================================================================
--======================= channel 5 hdlc txdata modulation ============================
Process(RST, CLK, Int5_reg)
begin
	if rst = '0' then
		Int5_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int5_reg(14 downto 0) = "011111011111100") then
			Int5_reg(16 downto 0) <= int5_reg(15) & "011111001111110" & txdata5a;
			
		else
			Int5_reg(16 downto 0) <= Int5_reg(15 downto 0) & txdata5a;
		end if;
	end if;
end process;

txdata5 <= int5_reg(16);
--=====================================================================================
--======================= channel 6 hdlc txdata modulation ============================
Process(RST, CLK, Int6_reg)
begin
	if rst = '0' then
		Int6_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int6_reg(14 downto 0) = "011111011111100") then
			Int6_reg(16 downto 0) <= int6_reg(15) & "011111001111110" & txdata6a;
			
		else
			Int6_reg(16 downto 0) <= Int6_reg(15 downto 0) & txdata6a;
		end if;
	end if;
end process;

txdata6 <= int6_reg(16);
--=====================================================================================
--======================= channel 7 hdlc txdata modulation ============================
Process(RST, CLK, Int7_reg)
begin
	if rst = '0' then
		Int7_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int7_reg(14 downto 0) = "011111011111100") then
			Int7_reg(16 downto 0) <= int7_reg(15) & "011111001111110" & txdata7a;
			
		else
			Int7_reg(16 downto 0) <= Int7_reg(15 downto 0) & txdata7a;
		end if;
	end if;
end process;

txdata7 <= int7_reg(16);
--=====================================================================================
--======================= channel 8 hdlc txdata modulation ============================
Process(RST, CLK, Int8_reg)
begin
	if rst = '0' then
		Int8_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int8_reg(14 downto 0) = "011111011111100") then
			Int8_reg(16 downto 0) <= int8_reg(15) & "011111001111110" & txdata8a;
			
		else
			Int8_reg(16 downto 0) <= Int8_reg(15 downto 0) & txdata8a;
		end if;
	end if;
end process;

txdata8 <= int8_reg(16);
--=====================================================================================
--======================= channel 9 hdlc txdata modulation ============================
Process(RST, CLK, Int9_reg)
begin
	if rst = '0' then
		Int9_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int9_reg(14 downto 0) = "011111011111100") then
			Int9_reg(16 downto 0) <= int9_reg(15) & "011111001111110" & txdata9a;
			
		else
			Int9_reg(16 downto 0) <= Int9_reg(15 downto 0) & txdata9a;
		end if;
	end if;
end process;

txdata9 <= int9_reg(16);
--=====================================================================================
--======================= channel 10 hdlc txdata modulation ============================
Process(RST, CLK, Int10_reg)
begin
	if rst = '0' then
		Int10_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int10_reg(14 downto 0) = "011111011111100") then
			Int10_reg(16 downto 0) <= int10_reg(15) & "011111001111110" & txdata10a;
			
		else
			Int10_reg(16 downto 0) <= Int10_reg(15 downto 0) & txdata10a;
		end if;
	end if;
end process;

txdata10 <= int10_reg(16);
--=====================================================================================
--======================= channel 11 hdlc txdata modulation ============================
Process(RST, CLK, Int11_reg)
begin
	if rst = '0' then
		Int11_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int11_reg(14 downto 0) = "011111011111100") then
			Int11_reg(16 downto 0) <= int11_reg(15) & "011111001111110" & txdata11a;
			
		else
			Int11_reg(16 downto 0) <= Int11_reg(15 downto 0) & txdata11a;
		end if;
	end if;
end process;

txdata11 <= int11_reg(16);
--=====================================================================================
--======================= channel 12 hdlc txdata modulation ============================
Process(RST, CLK, Int12_reg)
begin
	if rst = '0' then
		Int12_reg <= ( others => '0');
	elsif CLK'event and CLK = '0' then
		if (Int12_reg(14 downto 0) = "011111011111100") then
			Int12_reg(16 downto 0) <= int12_reg(15) & "011111001111110" & txdata12a;
			
		else
			Int12_reg(16 downto 0) <= Int12_reg(15 downto 0) & txdata12a;
		end if;
	end if;
end process;

txdata12 <= int12_reg(16);
--=====================================================================================



 	
CPU_CS <= CPU_CS0 and CPU_CS1;    	
 	


--======================== CPU bidirectional data control =================================

CPU_DATA <= CPU_DATA_L0 and CPU_DATA_L1 and CPU_DATA_L2 and CPU_DATA_L3 and CPU_DATA_L4 and
            CPU_DATA_L5 and CPU_DATA_L6 and CPU_DATA_L7 and CPU_DATA_L8 and CPU_DATA_L9 and
	    CPU_DATA_L10 and CPU_DATA_L11 and CPU_DATA_L12 when (RST = '1' and CPU_CS = '0' and CPU_WRn = '1') else "ZZZZZZZZ";

--=========================================================================================

--======================== CPU Interrupt control =================================

CPU_INTn <= CPU_INTn0 and CPU_INTn1 and CPU_INTn2 and CPU_INTn3 and CPU_INTn4 and CPU_INTn5 and CPU_INTn6 and
	    CPU_INTn7 and CPU_INTn8 and CPU_INTn9 and CPU_INTn10 and CPU_INTn11 and CPU_INTn12; 

--================================================================================



end HDLC_TOP_a;