📄 hdlc_top.vhd
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-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
-- Project: Single-Channel HDLC
-- File: HDLC_TOP.vhd
-- Title: HDLC_TOP
-- Design Library: IEEE
-- Dependencies: IEEE.std_logic_1164.all
-- IEEE.std_logic_unsigned.all
-- Description: Top VHDL file for 13 channels HDLC design
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--
-- Revision 1.0 2005-04-12 12:03:46-08 James Lee
-- Initial revision
--
-- --------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_Unsigned.all;
entity HDLC_TOP is
port (
-- Global Reset
RST : in std_logic; -- Master reset
-- CPU Interface
CPU_Data : inout std_logic_vector(7 downto 0); -- CPU data
CPU_Add : in std_logic_vector(7 downto 0); -- CPU address(7->24,6->25,5->26,4->27,3->28,2->29,1->30,0->31)
CPU_WRn : in std_logic; -- CPU Write/Read enable, When low, Write active
CPU_DSn : in std_logic; -- CPU Data Strobe, active low
CPU_CS0 : in std_logic; -- CPU Chip selection0
CPU_CS1 : in std_logic; -- CPU Chip selection1
CPU_INTn : out std_logic; -- CPU Interrupt
CPU_CLK : in std_logic; -- CPU clock
-- HDLC Clock
CLK : in std_logic;
-- HDLC Receive Serial Interface
RxData0 : in std_logic; -- Ch0 Receive Serial Data
RxData1 : in std_logic; -- Ch1 Receive Serial Data
RxData2 : in std_logic; -- Ch2 Receive Serial Data
RxData3 : in std_logic; -- Ch3 Receive Serial Data
RxData4 : in std_logic; -- Ch4 Receive Serial Data
RxData5 : in std_logic; -- Ch5 Receive Serial Data
RxData6 : in std_logic; -- Ch6 Receive Serial Data
RxData7 : in std_logic; -- Ch7 Receive Serial Data
RxData8 : in std_logic; -- Ch8 Receive Serial Data
RxData9 : in std_logic; -- Ch9 Receive Serial Data
RxData10 : in std_logic; -- Ch10 Receive Serial Data
RxData11 : in std_logic; -- Ch11 Receive Serial Data
RxData12 : in std_logic; -- Ch12 Receive Serial Data
-- HDLC Transmit Serial Interface
TxData0 : out std_logic; -- Ch0 Transmit Serial Data
TxData1 : out std_logic; -- Ch1 Transmit Serial Data
TxData2 : out std_logic; -- Ch2 Transmit Serial Data
TxData3 : out std_logic; -- Ch3 Transmit Serial Data
TxData4 : out std_logic; -- Ch4 Transmit Serial Data
TxData5 : out std_logic; -- Ch5 Transmit Serial Data
TxData6 : out std_logic; -- Ch6 Transmit Serial Data
TxData7 : out std_logic; -- Ch7 Transmit Serial Data
TxData8 : out std_logic; -- Ch8 Transmit Serial Data
TxData9 : out std_logic; -- Ch9 Transmit Serial Data
TxData10 : out std_logic; -- Ch10 Transmit Serial Data
TxData11 : out std_logic; -- Ch11 Transmit Serial Data
TxData12 : out std_logic); -- Ch12 Transmit Serial Data
--===============================================================
-- Pin Location
--===============================================================
attribute loc : string;
attribute loc of RST : signal is "M4";
attribute loc of CPU_Data : signal is "F1,E1,D1,H3,G2,H2,G1,J4";
attribute loc of CPU_Add : signal is "J3,J2,H1,K4,K5,K3,K2,J1";
attribute loc of CPU_WRn : signal is "M1";
attribute loc of CPU_DSn : signal is "L1"; -- this pin number changed L1 from M5, WS.Kim requested 17, Jun
attribute loc of CPU_CS0 : signal is "L4";
attribute loc of CPU_CS1 : signal is "L5";
attribute loc of CPU_INTn : signal is "V7";
attribute loc of CPU_CLK : signal is "L2";
attribute loc of CLK : signal is "K1";
attribute loc of RxData0 : signal is "V8";
attribute loc of RxData1 : signal is "W5";
attribute loc of RxData2 : signal is "AA3";
attribute loc of RxData3 : signal is "Y6";
attribute loc of RxData4 : signal is "AA5";
attribute loc of RxData5 : signal is "Y5";
attribute loc of RxData6 : signal is "AA4";
attribute loc of RxData7 : signal is "W10";
attribute loc of RxData8 : signal is "V10";
attribute loc of RxData9 : signal is "AA6";
attribute loc of RxData10 : signal is "AB5";
attribute loc of RxData11 : signal is "AA7";
attribute loc of RxData12 : signal is "AB7";
attribute loc of TxData0 : signal is "T6";
attribute loc of TxData1 : signal is "U7";
attribute loc of TxData2 : signal is "U6";
attribute loc of TxData3 : signal is "AB3";
attribute loc of TxData4 : signal is "V6";
attribute loc of TxData5 : signal is "W6";
attribute loc of TxData6 : signal is "Y4";
attribute loc of TxData7 : signal is "T9";
attribute loc of TxData8 : signal is "U10";
attribute loc of TxData9 : signal is "T10";
attribute loc of TxData10 : signal is "AA8";
attribute loc of TxData11 : signal is "AB6";
attribute loc of TxData12 : signal is "Y10";
--===============================================================
-- Pin IO type
--===============================================================
attribute IO_TYPE : string;
attribute IO_TYPE of RST : signal is "LVCMOS33";
attribute IO_TYPE of CPU_DATA : signal is "LVCMOS33";
attribute IO_TYPE of CPU_Add : signal is "LVCMOS33";
attribute IO_TYPE of CPU_DSn : signal is "LVCMOS33";
attribute IO_TYPE of CPU_CS0 : signal is "LVCMOS33";
attribute IO_TYPE of CPU_CS1 : signal is "LVCMOS33";
attribute IO_TYPE of CPU_INTn : signal is "LVCMOS33";
attribute IO_TYPE of CPU_CLK : signal is "LVCMOS33";
attribute IO_TYPE of CPU_WRn : signal is "LVCMOS33";
attribute IO_TYPE of CLK : signal is "LVCMOS33";
attribute IO_TYPE of RxData0 : signal is "LVCMOS33";
attribute IO_TYPE of RxData1 : signal is "LVCMOS33";
attribute IO_TYPE of RxData2 : signal is "LVCMOS33";
attribute IO_TYPE of RxData3 : signal is "LVCMOS33";
attribute IO_TYPE of RxData4 : signal is "LVCMOS33";
attribute IO_TYPE of RxData5 : signal is "LVCMOS33";
attribute IO_TYPE of RxData6 : signal is "LVCMOS33";
attribute IO_TYPE of RxData7 : signal is "LVCMOS33";
attribute IO_TYPE of RxData8 : signal is "LVCMOS33";
attribute IO_TYPE of RxData9 : signal is "LVCMOS33";
attribute IO_TYPE of RxData10 : signal is "LVCMOS33";
attribute IO_TYPE of RxData11 : signal is "LVCMOS33";
attribute IO_TYPE of RxData12 : signal is "LVCMOS33";
attribute IO_TYPE of TxData0 : signal is "LVCMOS33";
attribute IO_TYPE of TxData1 : signal is "LVCMOS33";
attribute IO_TYPE of TxData2 : signal is "LVCMOS33";
attribute IO_TYPE of TxData3 : signal is "LVCMOS33";
attribute IO_TYPE of TxData4 : signal is "LVCMOS33";
attribute IO_TYPE of TxData5 : signal is "LVCMOS33";
attribute IO_TYPE of TxData6 : signal is "LVCMOS33";
attribute IO_TYPE of TxData7 : signal is "LVCMOS33";
attribute IO_TYPE of TxData8 : signal is "LVCMOS33";
attribute IO_TYPE of TxData9 : signal is "LVCMOS33";
attribute IO_TYPE of TxData10 : signal is "LVCMOS33";
attribute IO_TYPE of TxData11 : signal is "LVCMOS33";
attribute IO_TYPE of TxData12 : signal is "LVCMOS33";
--=================================================================
end HDLC_TOP;
architecture HDLC_TOP_a of HDLC_TOP is
signal CPU_DATA_L0, CPU_DATA_L1, CPU_DATA_L2, CPU_DATA_L3, CPU_DATA_L4 : std_logic_vector(7 downto 0);
signal CPU_DATA_L5, CPU_DATA_L6, CPU_DATA_L7, CPU_DATA_L8, CPU_DATA_L9 : std_logic_vector(7 downto 0);
signal CPU_DATA_L10, CPU_DATA_L11, CPU_DATA_L12 : std_logic_vector(7 downto 0);
signal CPU_INTn0, CPU_INTn1, CPU_INTn2, CPU_INTn3, CPU_INTn4 : std_logic;
signal CPU_INTn5, CPU_INTn6, CPU_INTn7, CPU_INTn8, CPU_INTn9 : std_logic;
signal CPU_INTn10, CPU_INTn11, CPU_INTn12 : std_logic;
signal TxClk, RxClk : std_logic;
signal CPU_CS : std_logic;
signal DSn_sig1, DSn_sig2, DSn_sig3, DSn_sig4,DSn_sig5 : std_logic;
signal CH_clk, CH_DSn, CH_WR_DSn : std_logic;
signal CH_cs : std_logic_vector(12 downto 0);
signal testp : std_logic_vector(5 downto 0);
signal Clk_divide : std_logic_vector(3 downto 0);
signal CPU_DATA_a : std_logic_vector(7 downto 0);
signal CLK_OP, Inv_RST : std_logic;
signal txdata0a, txdata1a, txdata2a, txdata3a, txdata4a : std_logic;
signal txdata5a, txdata6a, txdata7a, txdata8a, txdata9a : std_logic;
signal txdata10a, txdata11a, txdata12a : std_logic;
signal TP_Test_P : std_logic_vector(4 downto 0);
signal bit_cnt : std_logic_vector(3 downto 0);
signal Int0_reg : std_logic_vector(16 downto 0);
signal Int1_reg : std_logic_vector(16 downto 0);
signal Int2_reg : std_logic_vector(16 downto 0);
signal Int3_reg : std_logic_vector(16 downto 0);
signal Int4_reg : std_logic_vector(16 downto 0);
signal Int5_reg : std_logic_vector(16 downto 0);
signal Int6_reg : std_logic_vector(16 downto 0);
signal Int7_reg : std_logic_vector(16 downto 0);
signal Int8_reg : std_logic_vector(16 downto 0);
signal Int9_reg : std_logic_vector(16 downto 0);
signal Int10_reg : std_logic_vector(16 downto 0);
signal Int11_reg : std_logic_vector(16 downto 0);
signal Int12_reg : std_logic_vector(16 downto 0);
type states is (idle, start, start1);
signal state_status : states;
COMPONENT SC_HDLC
PORT ( RST : in std_logic;
CPU_Data_in : in std_logic_vector(7 downto 0);
CPU_Data_out : out std_logic_vector(7 downto 0);
CPU_Add : in std_logic_vector(2 downto 0);
CPU_WRn : in std_logic;
CPU_DSn : in std_logic;
CPU_WR_DSn : in std_logic;
CPU_CS : in std_logic;
CPU_INTn : out std_logic;
CPU_clk : in std_logic;
RxClk : in std_logic;
RxData : in std_logic;
TxClk : in std_logic;
TxData : out std_logic);
END COMPONENT;
COMPONENT clk_pll
PORT (
CLKI :IN std_logic;
CLKFB :IN std_logic;
RST :IN std_logic;
CLKOP :OUT std_logic;
LOCK :OUT std_logic);
END COMPONENT;
begin
--================= Generate HDLC clock ==========================
Txclk <= clk;
RxClk <= clk;
--================================================================
--================== Generate Clock for CPU interace =============
Process(RST, CPU_clk)
begin
if rst = '0' then
Ch_clk <= '0';
elsif CPU_clk'event and CPU_clk = '1' then
Ch_clk <= not Ch_clk;
end if;
end process;
-- cpu clock is 50Mhz
-- but to improve timing margin, this logic is used 25Mhz
--================================================================
--================== Generate Data Strobe signal for Tx/Rx Fifo ===============
CH_DSn <= not(DSn_sig1 xor DSn_sig2) or CPU_DSn; -- Rx FIFO Read Enable
CH_WR_DSn <= not(DSn_sig2 xor DSn_sig3) or CPU_DSn; -- Tx FIFO Write Enable
Process(RST, CH_clk)
begin
if rst = '0' then
DSn_sig1 <= '0';
DSn_sig2 <= '0';
DSn_sig3 <= '0';
elsif CH_clk'event and CH_clk = '1' then
DSn_sig1 <= CPU_DSn;
DSn_sig2 <= DSn_sig1;
DSn_sig3 <= DSn_sig2;
end if;
end process;
--=============================================================================
--================= Generate Chennel selcet signal ==========================
Process(RST, CPU_clk, CPU_CS0, CPU_CS1)
begin
if rst = '0' then
CH_cs <= (others => '1');
elsif (CPU_clk'event and CPU_clk = '1') then
if (CPU_CS0 = '0' and CPU_CS1 = '1') then
case CPU_Add(6 downto 3) is -- Add7 -> 24, Add6 ->25, Add5 ->26, Add4 ->27, Add3 ->28
when "0000" => CH_cs <= "1111111111110"; -- Channel 1 chip seleciton enable
when "0010" => CH_cs <= "1111111111101"; -- Channel 2 chip seleciton enable
when "0100" => CH_cs <= "1111111111011"; -- Channel 3 chip seleciton enable
when "0110" => CH_cs <= "1111111110111"; -- Channel 4 chip seleciton enable
when "1000" => CH_cs <= "1111111101111"; -- Channel 5 chip seleciton enable
when "1010" => CH_cs <= "1111111011111"; -- Channel 6 chip seleciton enable
when "1100" => CH_cs <= "1111110111111"; -- Channel 7 chip seleciton enable
when "1110" => CH_cs <= "1111101111111"; -- Channel 8 chip seleciton enable
when others => CH_cs <= (others => '1');
end case;
elsif (CPU_CS0 = '1' and CPU_CS1 = '0') then
case CPU_Add(6 downto 3) is
when "0000" => CH_cs <= "1111011111111"; -- Channel 9 chip seleciton enable
when "0010" => CH_cs <= "1110111111111"; -- Channel 10 chip seleciton enable
when "0100" => CH_cs <= "1101111111111"; -- Channel 11 chip seleciton enable
when "0110" => CH_cs <= "1011111111111"; -- Channel 12 chip seleciton enable
when "1000" => CH_cs <= "0111111111111"; -- Channel 13 chip seleciton enable
when others => CH_cs <= (others => '1');
end case;
else
CH_cs <= (others => '1');
end if;
end if;
end process;
--============================================================================
--===================== Single channel HDLC mapping ==================================
CH0_Port : SC_HDLC
port map(
RST => RST,
CPU_Data_In => CPU_Data,
CPU_Data_Out => CPU_Data_L0,
CPU_Add => CPU_Add(2 downto 0),
CPU_WRn => CPU_WRn,
CPU_DSn => CH_DSn,
CPU_WR_DSn => CH_WR_DSn,
CPU_CS => CH_CS(0),
CPU_INTn => CPU_INTn0,
CPU_clk => CH_clk,
RxClk => RxClk,
RxData => RxData0,
TxClk => TxClk,
TxData => TxData0a);
CH1_Port : SC_HDLC
port map(
RST => RST,
CPU_Data_In => CPU_Data,
CPU_Data_Out => CPU_Data_L1,
CPU_Add => CPU_Add(2 downto 0),
CPU_WRn => CPU_WRn,
CPU_DSn => CH_DSn,
CPU_WR_DSn => CH_WR_DSn,
CPU_CS => CH_CS(1),
CPU_INTn => CPU_INTn1,
CPU_clk => CH_clk,
RxClk => RxClk,
RxData => RxData1,
TxClk => TxClk,
TxData => TxData1a);
CH2_Port : SC_HDLC
port map(
RST => RST,
CPU_Data_In => CPU_Data,
CPU_Data_Out => CPU_Data_L2,
CPU_Add => CPU_Add(2 downto 0),
CPU_WRn => CPU_WRn,
CPU_DSn => CH_DSn,
CPU_WR_DSn => CH_WR_DSn,
CPU_CS => CH_CS(2),
CPU_INTn => CPU_INTn2,
CPU_clk => CH_clk,
RxClk => RxClk,
RxData => RxData2,
TxClk => TxClk,
TxData => TxData2a);
CH3_Port : SC_HDLC
port map(
RST => RST,
CPU_Data_In => CPU_Data,
CPU_Data_Out => CPU_Data_L3,
CPU_Add => CPU_Add(2 downto 0),
CPU_WRn => CPU_WRn,
CPU_DSn => CH_DSn,
CPU_WR_DSn => CH_WR_DSn,
CPU_CS => CH_CS(3),
CPU_INTn => CPU_INTn3,
CPU_clk => CH_clk,
RxClk => RxClk,
RxData => RxData3,
TxClk => TxClk,
TxData => TxData3a);
CH4_Port : SC_HDLC
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