sn139sd.vhd

中科院VHDL学习资料

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sn139sd is
     Port (A1 : in bit;
           A2 : in bit;
           B1 : in bit;
           B2 : in bit;
           G1BAR : in bit;
           G2BAR : in bit;
           Y10 : out bit;
           Y11 : out bit;
           Y12 : out bit;
           Y13 : out bit;
           Y20 : out bit;
           Y21 : out bit;
           Y22 : out bit;
           Y23 : out bit);
end sn139sd;

entity inverter is
  port (
        g : in bit ;
        h : out bit) ;
  end inverter;
architecture behavior of inverter is
  begin
   process(g)
    begin
     h <= not(g); 
   end process;
end behavior; 

entity n_and3 is 
  port(a:in bit ;
       b:in bit ;
       c:in bit ;
		 d:out bit);
end n_and3;
architecture behavior of n_and3 is
  begin
   process(a,b,c)
    begin
     d <= not((a)and(b)and(c));
   end process;
end behavior;

architecture structural of sn139sd is

signal x  : bit_vector(0 to 5) ;

 component inverter
   port (g: in bit; h : out bit) ;
 end component;

 component n_and3
   port (a,b,c : in bit; d : out bit) ;
 end component;



 begin
 uo: inverter port map(g => G1BAR,h => x(0));
 u1: inverter port map(g => A1,h => x(1));
 u2: inverter port map(g => B1,h => x(2));
 u3: inverter port map(g => G2BAR,h => x(3));
 u4: inverter port map(g => A2,h => x(4));
 u5: inverter port map(g => B2,h => x(5));
 u6: n_and3 port map (a =>x(0) ,b=>x(1) ,c=>x(2) ,d=>Y10 );
 u7: n_and3 port map (a =>x(0) ,b=>A1 ,c=>x(2) ,d=>Y11 );
 u8: n_and3 port map (a =>x(0) ,b=>x(1) ,c=>B1 ,d=>Y12 );
 u9: n_and3 port map (a =>x(0) ,b=>A1,c=>B1 ,d=>Y13 );
 u10: n_and3 port map (a =>x(3) ,b=>x(4) ,c=>x(5) ,d=>Y20 );
 u11: n_and3 port map (a =>x(3) ,b=>A2 ,c=>x(5) ,d=>Y21 );
 u12: n_and3 port map (a =>x(3) ,b=>x(4) ,c=>B2 ,d=>Y22 );
 u13: n_and3 port map (a =>x(3) ,b=>A2,c=>B2 ,d=>Y23 );

end structural;