sn193dd.vhd

中科院VHDL学习资料

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SN193DD is
 Port (    A1 : in std_logic;
           A2 : in std_logic;
           B1 : in std_logic;
           B2 : in std_logic;
           G1BAR : in std_logic;
           G2BAR : in std_logic;
           Y10 : out std_logic;
           Y11 : out std_logic;
           Y12 : out std_logic;
           Y13 : out std_logic;
           Y20 : out std_logic;
           Y21 : out std_logic;
           Y22 : out std_logic;
           Y23 : out std_logic);
end SN193DD;

architecture DD of SN193DD is

begin
  Y10 <=not(not(A1) and not(B1) and not(G1BAR));
  Y11 <=not((A1) and not(B1) and not(G1BAR));
  Y12 <=not(not(A1) and (B1) and not(G1BAR));
  Y13 <=not((A1) and (B1) and not(G1BAR));
  Y20 <=not(not(A2) and not(B2) and not(G2BAR));
  Y21 <=not((A2) and not(B2) and not(G2BAR));
  Y22 <=not(not(A2) and (B2) and not(G2BAR));
  Y23 <=not((A2) and (B2) and not(G2BAR));
end DD;