sn139bd.vhd

来自「中科院VHDL学习资料」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SN139BD is
    Port ( A1 : in std_logic;
           A2 : in std_logic;
           B1 : in std_logic;
           B2 : in std_logic;
           G1BAR : in std_logic;
           G2BAR : in std_logic;
           Y10 : out std_logic;
           Y11 : out std_logic;
           Y12 : out std_logic;
           Y13 : out std_logic;
           Y20 : out std_logic;
           Y21 : out std_logic;
           Y22 : out std_logic;
           Y23 : out std_logic);
end SN139BD;

architecture BD of SN139BD is

begin
Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';
Y11 <= '0' when (B1 = '0') and ((A1 = '1') and (G1BAR = '0')) else '1';
Y12 <= '0' when (B1 = '1') and ((A1 = '0') and (G1BAR = '0')) else '1';
Y13 <= '0' when (B1 = '1') and ((A1 = '1') and (G1BAR = '0')) else '1';
Y20 <= '0' when (B2 = '0') and ((A2 = '0') and (G2BAR = '0')) else '1';
Y21 <= '0' when (B2 = '0') and ((A2 = '1') and (G2BAR = '0')) else '1';
Y22 <= '0' when (B2 = '1') and ((A2 = '0') and (G2BAR = '0')) else '1';
Y23 <= '0' when (B2 = '1') and ((A2 = '1') and (G2BAR = '0')) else '1';

end BD;