reg10b.vhd

来自「fpga 控制dds 程序。希望对各位有用」· VHDL 代码 · 共 15 行

library ieee;
use ieee.std_logic_1164.all
entity reg10b is
   port(  load:in std_logic_vector(9 downto 0);
          din:in std_logic_vector(9 downto 0);
          dout:out std_logic_vector(9 downto 0));
architecture behav of reg10b is
    process(load,din)
  begin 
  if load'event and load='1' then dout<=din;end if;
    end process;
end behav;