sin_rom.vhd

来自「fpga 控制dds 程序。希望对各位有用」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
entity sin_rom is
   port(address:in std_logic_vector(9 downto 0);
        inclockLin std_logic;
        q:out std_logic_vector(9 downto 0));
end sin_rom;
architecture syn of sin_rom is
signal sub_wire0:std_logic_vector(9 downto 0);
component lpm_rom
generic(lpm_width:natural;
        lpm_widthad:natural;
        lpm_address_control:string;
        lpm_outdata:string;
        lpm_file:string;
 port (address:in std_logic_vectoe(9 downto 0);
       inclock:in std_logic;
             q:out std_logic_vector(9 downto 0);
 end port;
begin
   q<=sub_wire0(9 downto 0);
   lpm_rom_component:lpm_rom generic map(lpm_width=>10,
              lpm_widthad=>10,lpm_address_control=>"registered",
              lpm_file=>"lut10x10.mif")
    port map(address=>address, inclock=>inclock,q=>sub_wire0);
end syn;